From 04a9360d85772e7949121fafc2eb7f09c6416be8 Mon Sep 17 00:00:00 2001 From: sbwml Date: Thu, 13 Jun 2024 19:41:45 +0800 Subject: [PATCH] rockchip: rk356x adjust CPU voltage Signed-off-by: sbwml --- .../dts/rockchip/rk3568-nanopi-common.dtsi | 62 ++++------ .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +- ...d-support-for-modifying-IRQ-affinity.patch | 4 +- ...3-rockchip-rk356x-adjust-CPU-voltage.patch | 116 ++++++++++++++++++ 4 files changed, 142 insertions(+), 42 deletions(-) create mode 100644 patches-6.6/993-rockchip-rk356x-adjust-CPU-voltage.patch diff --git a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi index 2fd62a6..e94fd00 100644 --- a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi +++ b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi @@ -78,26 +78,6 @@ vin-supply = <&vdd_usbc>; }; - pcie30_avdd0v9: pcie30-avdd0v9 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8 { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie"; @@ -109,17 +89,6 @@ vin-supply = <&vcc5v0_sys>; }; - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <50000>; - vin-supply = <&vcc3v3_pcie>; - }; - vcc3v3_ngff: vcc3v3-ngff-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_ngff"; @@ -148,6 +117,8 @@ pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_usb_host_en>; regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; @@ -174,6 +145,26 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc3v3_sys>; }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; }; &combphy0 { @@ -242,7 +233,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; regulator-ramp-delay = <2300>; vin-supply = <&vcc5v0_sys>; @@ -276,7 +267,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -290,7 +280,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -314,7 +303,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -339,7 +327,6 @@ vdda0v9_image: LDO_REG1 { regulator-name = "vdda0v9_image"; - regulator-always-on; regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>; @@ -375,8 +362,6 @@ vccio_acodec: LDO_REG4 { regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -435,7 +420,6 @@ vcca1v8_image: LDO_REG9 { regulator-name = "vcca1v8_image"; - regulator-always-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts index 687c5b5..c868ee0 100644 --- a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +++ b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts @@ -109,7 +109,7 @@ rockchip-key { reset_button_pin: reset-button-pin { - rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; }; }; }; diff --git a/patches-6.6/950-nvme-pci-add-support-for-modifying-IRQ-affinity.patch b/patches-6.6/950-nvme-pci-add-support-for-modifying-IRQ-affinity.patch index c4fe663..6c7ff3e 100644 --- a/patches-6.6/950-nvme-pci-add-support-for-modifying-IRQ-affinity.patch +++ b/patches-6.6/950-nvme-pci-add-support-for-modifying-IRQ-affinity.patch @@ -26,7 +26,7 @@ Signed-off-by: sbwml qoff += map->nr_queues; offset += map->nr_queues; } -@@ -2217,6 +2214,8 @@ static int nvme_setup_irqs(struct nvme_d +@@ -2223,6 +2220,8 @@ static int nvme_setup_irqs(struct nvme_d }; unsigned int irq_queues, poll_queues; unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY; @@ -35,7 +35,7 @@ Signed-off-by: sbwml /* * Poll queues don't need interrupts, but we need at least one I/O queue -@@ -2242,8 +2241,19 @@ static int nvme_setup_irqs(struct nvme_d +@@ -2248,8 +2247,19 @@ static int nvme_setup_irqs(struct nvme_d irq_queues += (nr_io_queues - poll_queues); if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) flags &= ~PCI_IRQ_MSI; diff --git a/patches-6.6/993-rockchip-rk356x-adjust-CPU-voltage.patch b/patches-6.6/993-rockchip-rk356x-adjust-CPU-voltage.patch new file mode 100644 index 0000000..c07ce31 --- /dev/null +++ b/patches-6.6/993-rockchip-rk356x-adjust-CPU-voltage.patch @@ -0,0 +1,116 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -233,7 +233,7 @@ + &cpu0_opp_table { + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1150000 1150000 1150000>; ++ opp-microvolt = <1250000>; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -93,39 +93,39 @@ + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <1000000 975000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <1000000 975000 1150000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <1000000 975000 1150000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <1000000 975000 1150000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <1000000 975000 1150000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <975000 975000 1150000>; ++ opp-microvolt = <1000000 1000000 1150000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <1050000 1050000 1150000>; ++ opp-microvolt = <1150000 1000000 1250000>; + }; + }; + +--- a/drivers/clk/rockchip/clk-rk3568.c ++++ b/drivers/clk/rockchip/clk-rk3568.c +@@ -158,16 +158,17 @@ static struct rockchip_pll_rate_table rk + } + + static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { ++ RK3568_CPUCLK_RATE(1992000000, 0, 1, 8, 8, 8, 8), + RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), + RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), +- RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5), ++ RK3568_CPUCLK_RATE(1608000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1584000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1560000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1536000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1512000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1488000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1464000000, 0, 1, 6, 6, 6, 6), ++ RK3568_CPUCLK_RATE(1440000000, 0, 1, 6, 6, 6, 6), + RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5), +@@ -177,17 +178,17 @@ static struct rockchip_cpuclk_rate_table + RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5), + RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5), +- RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3), ++ RK3568_CPUCLK_RATE(1200000000, 0, 1, 4, 4, 4, 4), ++ RK3568_CPUCLK_RATE(1104000000, 0, 1, 4, 4, 4, 4), ++ RK3568_CPUCLK_RATE(1008000000, 0, 1, 4, 4, 4, 4), + RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3), +- RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3), ++ RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 2), ++ RK3568_CPUCLK_RATE(696000000, 0, 1, 2, 2, 2, 2), ++ RK3568_CPUCLK_RATE(600000000, 0, 1, 2, 2, 2, 2), ++ RK3568_CPUCLK_RATE(408000000, 0, 1, 1, 1, 1, 1), ++ RK3568_CPUCLK_RATE(312000000, 0, 1, 1, 1, 1, 1), ++ RK3568_CPUCLK_RATE(216000000, 0, 1, 1, 1, 1, 1), ++ RK3568_CPUCLK_RATE(96000000, 0, 1, 1, 1, 1, 1), + }; + + static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {