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rockchip: dts: add OF node for NanoPi R5S

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Signed-off-by: sbwml <admin@cooluc.com>
This commit is contained in:
sbwml 2024-07-05 23:54:16 +08:00
parent 0526aea92c
commit 104f14408b
2 changed files with 70 additions and 32 deletions
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13
files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
View File

@ -73,6 +73,19 @@
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie-eth@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x0 0x0 0x2b 0x200>;
};
};
};
&pcie3x2 {

87
files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
View File

@ -67,67 +67,98 @@
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
reg = <1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
pinctrl-0 = <&gmac_int>;
realtek,led-data = <0x6d60>;
};
};
&pcie2x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
pcie@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_1: pcie@1,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x0 0x0 0x2b 0x200>;
};
};
};
&pcie30phy {
data-lanes = <1 2>;
status = "okay";
};
&pcie3x1 {
num-lanes = <1>;
// reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_ngff>;
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
pcie@0,0 {
reg = <0x00100000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
rtl8125_2: pcie@10,0 {
compatible = "pci10ec,8125";
reg = <0x000000 0 0 0 0>;
realtek,led-data = <0x0 0x0 0x2b 0x200>;
};
};
};
&pcie3x2 {
num-lanes = <1>;
num-ib-windows = <8>;
num-ob-windows = <8>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie2x1 {
num-viewport = <4>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
&pinctrl {
gpio-leds {
sys_led_pin: sys-led-pin {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -145,12 +176,6 @@
};
};
gmac {
gmac_int: gmac-int {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
gpio-key {
key1_pin: key1-pin {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;