zhao/target_linux_rockchip-6.x
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rockchip: remove linux-6.3

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sbwml 2023-06-24 12:28:28 +08:00
parent 7e0dfd4120
commit 4bbbd1752b
26 changed files with 0 additions and 3911 deletions
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1
Makefile
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@ -8,7 +8,6 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
SUBTARGETS:=armv8
KERNEL_PATCHVER:=6.1
KERNEL_TESTING_PATCHVER:=6.3
define Target/Description
Build firmware image for Rockchip SoC devices.

859
armv8/config-6.3
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@ -1,859 +0,0 @@
CONFIG_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_ARC_EMAC_CORE=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_EPAN=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1530923=y
CONFIG_ARM64_ERRATUM_2051678=y
CONFIG_ARM64_ERRATUM_2077057=y
CONFIG_ARM64_ERRATUM_2441009=y
CONFIG_ARM64_ERRATUM_819472=y
CONFIG_ARM64_ERRATUM_824069=y
CONFIG_ARM64_ERRATUM_826319=y
CONFIG_ARM64_ERRATUM_827319=y
CONFIG_ARM64_ERRATUM_832075=y
CONFIG_ARM64_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_845719=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PAN=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_PTR_AUTH_KERNEL=y
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_SME=y
CONFIG_ARM64_SVE=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_VA_BITS=48
# CONFIG_ARM64_VA_BITS_39 is not set
CONFIG_ARM64_VA_BITS_48=y
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
# CONFIG_ARMV8_DEPRECATED is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_FFA_SMCCC=y
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_MHU=y
CONFIG_ARM_MHU_V2=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_POWER_CONTROL=y
CONFIG_ARM_SCMI_POWER_DOMAIN=y
CONFIG_ARM_SCMI_PROTOCOL=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
CONFIG_ARM_SCPI_CPUFREQ=y
CONFIG_ARM_SCPI_POWER_DOMAIN=y
CONFIG_ARM_SCPI_PROTOCOL=y
CONFIG_ARM_SMCCC_SOC_ID=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
CONFIG_ATA=y
CONFIG_ATA_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_BINARY_PRINTF=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_BSG_COMMON=y
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_INTEGRITY_T10=y
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_MD is not set
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_COMPAT=y
CONFIG_BLOCK_LEGACY_AUTOLOAD=y
CONFIG_BRCMSTB_GISB_ARB=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
# CONFIG_CACHEFILES_ERROR_INJECTION is not set
# CONFIG_CACHEFILES_ONDEMAND is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
CONFIG_CHARGER_GPIO=y
CONFIG_CHR_DEV_SG=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLK_PX30=y
CONFIG_CLK_RK3308=y
CONFIG_CLK_RK3328=y
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
CONFIG_CLK_RK3568=y
CONFIG_CLK_RK3588=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMA=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_ROCKCHIP=y
# CONFIG_COMMON_CLK_RS9_PCIE is not set
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
CONFIG_COMPAT=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_CONFIGFS_FS=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CONTIG_ALLOC=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_FREQ=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_ISOLATION=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRASH_CORE=y
CONFIG_CRASH_DUMP=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC64=y
CONFIG_CRC64_ROCKSOFT=y
CONFIG_CRC7=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC_T10DIF=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_CRYPTO_AES_ARM64=y
CONFIG_CRYPTO_AES_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DEV_ROCKCHIP2=y
# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
CONFIG_CRYPTO_ENGINE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_SM3_GENERIC=y
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_USERSPACE=y
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DEVMEM=y
# CONFIG_DEVPORT is not set
# CONFIG_DM9051 is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_CMA=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DNOTIFY=y
CONFIG_DTC=y
CONFIG_DT_IDLE_GENPD=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_DWMAC_GENERIC=y
CONFIG_DWMAC_ROCKCHIP=y
CONFIG_DW_WATCHDOG=y
# CONFIG_DRM_ANALOGIX_ANX7625 is not set
# CONFIG_DRM_CHIPONE_ICN6211 is not set
# CONFIG_DRM_ITE_IT6505 is not set
# CONFIG_DRM_ITE_IT66121 is not set
# CONFIG_DRM_LONTIUM_LT8912B is not set
# CONFIG_DRM_LONTIUM_LT9211 is not set
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
# CONFIG_DRM_PANEL_DSI_CM is not set
# CONFIG_DRM_PANEL_EDP is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
# CONFIG_DRM_PANEL_JDI_R63452 is not set
# CONFIG_DRM_PANEL_KHADAS_TS050 is not set
# CONFIG_DRM_PANEL_MIPI_DBI is not set
# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set
# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set
# CONFIG_DRM_RCAR_USE_LVDS is not set
# CONFIG_DRM_SIMPLEDRM is not set
# CONFIG_DRM_SSD130X is not set
# CONFIG_DRM_TI_SN65DSI83 is not set
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_EMAC_ROCKCHIP=y
CONFIG_ENERGY_MODEL=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXTCON=y
CONFIG_F2FS_FS=y
CONFIG_FANOTIFY=y
CONFIG_FB_CMDLINE=y
CONFIG_FHANDLE=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
# CONFIG_FORTIFY_SOURCE is not set
CONFIG_FRAME_POINTER=y
CONFIG_FRAME_WARN=2048
# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
# CONFIG_FUN_ETH is not set
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_ROCKCHIP=y
# CONFIG_GPIO_SIM is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
# CONFIG_HARDENED_USERCOPY is not set
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_HAS_IOPORT_MAP is not set
CONFIG_HID=y
CONFIG_HID_GENERIC=y
# CONFIG_HISI_PTT is not set
CONFIG_HOTPLUG_CPU=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_HOTPLUG_PCI_SHPC=y
# CONFIG_HP_WATCHDOG is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HW_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_I2C=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_PCI1XXXX is not set
CONFIG_I2C_RK3X=y
# CONFIG_IIO_SCMI is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INDIRECT_PIO=y
CONFIG_INET_TABLE_PERTURB_ORDER=16
CONFIG_INPUT=y
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_KEYBOARD=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_MOUSE=y
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_RK805_PWRKEY=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_IOMMU_API=y
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
CONFIG_IOMMU_DMA=y
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_IO_PGTABLE=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IO_STRICT_DEVMEM is not set
CONFIG_IO_URING=y
# CONFIG_IR_GPIO_TX is not set
# CONFIG_IR_IMON_DECODER is not set
# CONFIG_IR_IMON_RAW is not set
# CONFIG_IR_MCE_KBD_DECODER is not set
# CONFIG_IR_PWM_TX is not set
# CONFIG_IR_RCMM_DECODER is not set
# CONFIG_IR_SANYO_DECODER is not set
# CONFIG_IR_SERIAL is not set
# CONFIG_IR_SHARP_DECODER is not set
# CONFIG_IR_SPI is not set
# CONFIG_IR_TOY is not set
# CONFIG_IR_XMP_DECODER is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JUMP_LABEL=y
CONFIG_KALLSYMS=y
CONFIG_KCMP=y
CONFIG_KEXEC_CORE=y
CONFIG_KEXEC_FILE=y
# CONFIG_KEXEC_SIG is not set
CONFIG_KSM=y
CONFIG_KVM=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_VFIO=y
# CONFIG_LAN966X_SWITCH is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_PWM=y
# CONFIG_LEDS_PWM_MULTICOLOR is not set
CONFIG_LEDS_SYSCON=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_LIBCRC32C=y
CONFIG_LIBFDT=y
CONFIG_LOCALVERSION_AUTO=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LOG_BUF_SHIFT=19
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_BUS_MUX=y
CONFIG_MDIO_BUS_MUX_GPIO=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MEDIATEK_GE_PHY=y
CONFIG_MEMFD_CREATE=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_MAX77714 is not set
# CONFIG_MFD_MT6370 is not set
CONFIG_MFD_RK808=y
# CONFIG_MFD_RT5120 is not set
# CONFIG_MFD_SY7636A is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_CQHCI=y
CONFIG_MMC_DW=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
CONFIG_MMC_DW_PCI=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SDHCI_F_SDH30=y
CONFIG_MMC_SDHCI_OF_ARASAN=y
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SPI=y
CONFIG_MMC_USDHI6ROL0=y
CONFIG_MMC_USHC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_MOTORCOMM_PHY=y
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_CYPRESS=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
CONFIG_MQ_IOSCHED_DEADLINE=y
# CONFIG_MTD_CFI is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_MT7530=y
# CONFIG_NET_DSA_REALTEK is not set
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
# CONFIG_NFSD_V4_2_INTER_SSC is not set
CONFIG_NLS=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
# CONFIG_NVMEM_ROCKCHIP_EFUSE is not set
# CONFIG_NVMEM_ROCKCHIP_OTP is not set
# CONFIG_NVMEM_U_BOOT_ENV is not set
# CONFIG_NVHE_EL2_DEBUG is not set
# CONFIG_OCTEON_EP is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IOMMU=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_RESOLVE=y
CONFIG_OLD_SIGSUSPEND3=y
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEFAULT is not set
CONFIG_PCIEASPM_EXT=y
CONFIG_PCIEASPM_PERFORMANCE=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_ROCKCHIP=y
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
CONFIG_PCIE_ROCKCHIP_HOST=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_STUB=y
CONFIG_PCS_XPCS=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_PHY_ROCKCHIP_DP=y
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
CONFIG_PHY_ROCKCHIP_EMMC=y
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
CONFIG_PHY_ROCKCHIP_PCIE=y
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_PHY_ROCKCHIP_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_RK805=y
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PL330_DMA=y
CONFIG_PLATFORM_MHU=y
CONFIG_PM=y
CONFIG_PM_CLK=y
CONFIG_PM_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
CONFIG_PM_GENERIC_DOMAINS=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PM_OPP=y
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_POWER_RESET=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_HWMON=y
CONFIG_PPS=y
CONFIG_PREEMPT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_COUNT=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_RCU=y
CONFIG_PRINTK_TIME=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_VMCORE=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_PWM=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SYSFS=y
# CONFIG_PWM_XILINX is not set
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_QUOTA=y
CONFIG_QUOTACTL=y
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
CONFIG_RAID_ATTRS=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_RC_XBOX_DVD is not set
CONFIG_RCU_TRACE=y
CONFIG_REALTEK_PHY=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_ARM_SCMI is not set
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
# CONFIG_REGULATOR_RT5190A is not set
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_TPS6286X is not set
CONFIG_RELOCATABLE=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_SCMI=y
CONFIG_RFS_ACCEL=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_ROCKCHIP_ERRATUM_114514=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IOMMU=y
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_MBOX=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
# CONFIG_ROCKCHIP_RGB is not set
CONFIG_ROCKCHIP_THERMAL=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_ROCKCHIP_VOP=y
CONFIG_ROCKCHIP_VOP2=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPS=y
CONFIG_RSEQ=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_RK808=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_NVMEM=y
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCSI=y
CONFIG_SCSI_COMMON=y
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_PROC_FS is not set
# CONFIG_SCSI_SAS_ATA is not set
CONFIG_SCSI_SAS_ATTRS=y
CONFIG_SCSI_SAS_HOST_SMP=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SDIO_UART=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SENSORS_ARM_SCMI=y
CONFIG_SENSORS_ARM_SCPI=y
# CONFIG_SENSORS_NCT6775_I2C is not set
# CONFIG_SENSORS_TMP464 is not set
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_DWLIB=y
CONFIG_SERIAL_8250_EXAR=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_FINTEK=y
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIO=y
CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_PCIPS2=y
CONFIG_SERIO_RAW=y
# CONFIG_SFC_SIENA is not set
CONFIG_SG_POOL=y
# CONFIG_SHADOW_CALL_STACK is not set
CONFIG_SLUB_DEBUG=y
CONFIG_SMP=y
# CONFIG_SND_SOC_ROCKCHIP is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_DYNAMIC=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_SPIDEV=y
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SRAM=y
CONFIG_SRCU=y
CONFIG_STACKDEPOT=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_STACKTRACE=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
# CONFIG_STMMAC_SELFTESTS is not set
CONFIG_STRICT_DEVMEM=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_SWAP is not set
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYNC_FILE=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_SYSVIPC_COMPAT=y
# CONFIG_TEXTSEARCH is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_EMULATION=y
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
# CONFIG_TINYDRM_ILI9163 is not set
CONFIG_TRACE_CLOCK=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_TRANS_TABLE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_TYPEC=y
# CONFIG_TYPEC_ANX7411 is not set
# CONFIG_TYPEC_DP_ALTMODE is not set
CONFIG_TYPEC_FUSB302=y
# CONFIG_TYPEC_HD3SS3220 is not set
# CONFIG_TYPEC_MUX_FSA4480 is not set
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# CONFIG_TYPEC_RT1719 is not set
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_TCPCI is not set
CONFIG_TYPEC_TCPM=y
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_TYPEC_WUSB3801 is not set
# CONFIG_UACCE is not set
# CONFIG_UCLAMP_TASK is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_HOST=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_HID=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_PHY=y
CONFIG_USB_ROLE_SWITCH=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USERIO=y
CONFIG_VENDOR_FRIENDLYELEC=y
CONFIG_VIDEOMODE_HELPERS=y
# CONFIG_VIRTIO_MENU is not set
CONFIG_VIRTUALIZATION=y
CONFIG_VMAP_STACK=y
# CONFIG_VMWARE_VMCI is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XARRAY_MULTI=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y

13
patches-6.3/001-gpio-sysfs-build.patch
View File

@ -1,13 +0,0 @@
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0642f5791..830bc9a8e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -59,7 +59,7 @@ config DEBUG_GPIO
that are most common when setting up new platforms or boards.
config GPIO_SYSFS
- bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
+ bool "/sys/class/gpio/... (sysfs interface)"
depends on SYSFS
select GPIO_CDEV # We need to encourage the new ABI
help

398
patches-6.3/002-add-hwrng-for-rk3568.patch
View File

@ -1,398 +0,0 @@
From 7592a44966f7c135d4460b564fcd8d39fe323b68 Mon Sep 17 00:00:00 2001
From: sbwml <984419930@qq.com>
Date: Sat, 31 Dec 2022 18:42:34 +0800
Subject: [PATCH] add hwrng for rk3568
---
.../bindings/rng/rockchip,rk3568-rng.yaml | 60 +++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +
drivers/char/hw_random/Kconfig | 14 +
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/rk3568-rng.c | 250 ++++++++++++++++++
5 files changed, 335 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
create mode 100644 drivers/char/hw_random/rk3568-rng.c
diff --git a/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
new file mode 100644
index 000000000..c2f5ef69c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip TRNG
+
+description: True Random Number Generator for some Rockchip SoCs
+
+maintainers:
+ - Aurelien Jarno <aurelien@aurel32.net>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-rng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: TRNG clock
+ - description: TRNG AHB clock
+
+ clock-names:
+ items:
+ - const: trng_clk
+ - const: trng_hclk
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rng@fe388000 {
+ compatible = "rockchip,rk3568-rng";
+ reg = <0x0 0xfe388000 0x0 0x4000>;
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+ clock-names = "trng_clk", "trng_hclk";
+ resets = <&cru SRST_TRNG_NS>;
+ };
+ };
+
+...
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 164708f1e..718171234 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1770,6 +1770,16 @@ usb2phy1_otg: otg-port {
};
};
+ rng: rng@fe388000 {
+ compatible = "rockchip,rk3568-rng";
+ reg = <0x0 0xfe388000 0x0 0x4000>;
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
+ clock-names = "trng_clk", "trng_hclk";
+ resets = <&cru SRST_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 3da8e85f8..3e20e4421 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -372,6 +372,20 @@ config HW_RANDOM_STM32
If unsure, say N.
+config HW_RANDOM_ROCKCHIP_RK3568
+ tristate "Rockchip RK3568 True Random Number Generator"
+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
+ depends on HAS_IOMEM
+ default HW_RANDOM
+ help
+ This driver provides kernel-side support for the True Random Number
+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
+
+ To compile this driver as a module, choose M here: the
+ module will be called rockchip-rng.
+
+ If unsure, say Y.
+
config HW_RANDOM_PIC32
tristate "Microchip PIC32 Random Number Generator support"
depends on HW_RANDOM && MACH_PIC32
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 3e948cf04..460191bcf 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP_RK3568) += rk3568-rng.o
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
diff --git a/drivers/char/hw_random/rk3568-rng.c b/drivers/char/hw_random/rk3568-rng.c
new file mode 100644
index 000000000..b04346b23
--- /dev/null
+++ b/drivers/char/hw_random/rk3568-rng.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
+ *
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022, Aurelien Jarno
+ * Authors:
+ * Lin Jinhan <troy.lin@rock-chips.com>
+ * Aurelien Jarno <aurelien@aurel32.net>
+ */
+#include <linux/clk.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#define RK_RNG_AUTOSUSPEND_DELAY 100
+#define RK_RNG_MAX_BYTE 32
+#define RK_RNG_POLL_PERIOD_US 100
+#define RK_RNG_POLL_TIMEOUT_US 10000
+
+/*
+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
+ * a tradeoff between speed and quality and has been adjusted to get a quality
+ * of ~900 (~90% of FIPS 140-2 successes).
+ */
+#define RK_RNG_SAMPLE_CNT 1000
+
+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
+#define TRNG_RST_CTL 0x0004
+#define TRNG_RNG_CTL 0x0400
+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
+#define TRNG_RNG_CTL_ENABLE BIT(1)
+#define TRNG_RNG_CTL_START BIT(0)
+#define TRNG_RNG_SAMPLE_CNT 0x0404
+#define TRNG_RNG_DOUT_0 0x0410
+#define TRNG_RNG_DOUT_1 0x0414
+#define TRNG_RNG_DOUT_2 0x0418
+#define TRNG_RNG_DOUT_3 0x041c
+#define TRNG_RNG_DOUT_4 0x0420
+#define TRNG_RNG_DOUT_5 0x0424
+#define TRNG_RNG_DOUT_6 0x0428
+#define TRNG_RNG_DOUT_7 0x042c
+
+struct rk_rng {
+ struct hwrng rng;
+ void __iomem *base;
+ struct reset_control *rst;
+ int clk_num;
+ struct clk_bulk_data *clk_bulks;
+};
+
+/* The mask determine the bits that are updated */
+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
+{
+ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
+}
+
+static int rk_rng_init(struct hwrng *rng)
+{
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ u32 reg;
+ int ret;
+
+ /* start clocks */
+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
+ if (ret < 0) {
+ dev_err((struct device *) rk_rng->rng.priv,
+ "Failed to enable clks %d\n", ret);
+ return ret;
+ }
+
+ /* set the sample period */
+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
+
+ /* set osc ring speed and enable it */
+ reg = TRNG_RNG_CTL_LEN_256_BIT |
+ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
+ TRNG_RNG_CTL_ENABLE;
+ rk_rng_write_ctl(rk_rng, reg, 0xffff);
+
+ return 0;
+}
+
+static void rk_rng_cleanup(struct hwrng *rng)
+{
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ u32 reg;
+
+ /* stop TRNG */
+ reg = 0;
+ rk_rng_write_ctl(rk_rng, reg, 0xffff);
+
+ /* stop clocks */
+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
+}
+
+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ u32 reg;
+ int ret = 0;
+ int i;
+
+ pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
+
+ /* Start collecting random data */
+ reg = TRNG_RNG_CTL_START;
+ rk_rng_write_ctl(rk_rng, reg, reg);
+
+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
+ !(reg & TRNG_RNG_CTL_START),
+ RK_RNG_POLL_PERIOD_US,
+ RK_RNG_POLL_TIMEOUT_US);
+ if (ret < 0)
+ goto out;
+
+ /* Read random data stored in the registers */
+ ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
+ for (i = 0; i < ret; i += 4) {
+ *(u32 *)(buf + i) = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
+ }
+
+out:
+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
+
+ return ret;
+}
+
+static int rk_rng_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rk_rng *rk_rng;
+ int ret;
+
+ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
+ if (!rk_rng)
+ return -ENOMEM;
+
+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rk_rng->base))
+ return PTR_ERR(rk_rng->base);
+
+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
+ if (rk_rng->clk_num < 0)
+ return dev_err_probe(dev, rk_rng->clk_num,
+ "Failed to get clks property\n");
+
+ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
+ if (IS_ERR(rk_rng->rst))
+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
+ "Failed to get reset property\n");
+
+ reset_control_assert(rk_rng->rst);
+ udelay(2);
+ reset_control_deassert(rk_rng->rst);
+
+ platform_set_drvdata(pdev, rk_rng);
+
+ rk_rng->rng.name = dev_driver_string(dev);
+#ifndef CONFIG_PM
+ rk_rng->rng.init = rk_rng_init;
+ rk_rng->rng.cleanup = rk_rng_cleanup;
+#endif
+ rk_rng->rng.read = rk_rng_read;
+ rk_rng->rng.priv = (unsigned long) dev;
+ rk_rng->rng.quality = 900;
+
+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_enable(dev);
+
+ ret = devm_hwrng_register(dev, &rk_rng->rng);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
+
+ dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
+
+ return 0;
+}
+
+static int rk_rng_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int rk_rng_runtime_suspend(struct device *dev)
+{
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+ rk_rng_cleanup(&rk_rng->rng);
+
+ return 0;
+}
+
+static int rk_rng_runtime_resume(struct device *dev)
+{
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+ return rk_rng_init(&rk_rng->rng);
+}
+#endif
+
+static const struct dev_pm_ops rk_rng_pm_ops = {
+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
+ rk_rng_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+};
+
+static const struct of_device_id rk_rng_dt_match[] = {
+ {
+ .compatible = "rockchip,rk3568-rng",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
+
+static struct platform_driver rk_rng_driver = {
+ .driver = {
+ .name = "rk3568-rng",
+ .pm = &rk_rng_pm_ops,
+ .of_match_table = rk_rng_dt_match,
+ },
+ .probe = rk_rng_probe,
+ .remove = rk_rng_remove,
+};
+
+module_platform_driver(rk_rng_driver);
+
+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
+MODULE_LICENSE("GPL v2");
--
2.34.1

439
patches-6.3/003-rk3568-general-patch-set.patch
View File

@ -1,439 +0,0 @@
diff -Naur a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
--- a/drivers/clk/rockchip/clk-half-divider.c 2022-07-31 17:03:01.000000000 -0400
+++ b/drivers/clk/rockchip/clk-half-divider.c 2022-08-09 17:00:56.992472371 -0400
@@ -166,7 +166,7 @@
unsigned long flags,
spinlock_t *lock)
{
- struct clk_hw *hw = ERR_PTR(-ENOMEM);
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
diff -Naur a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
--- a/drivers/usb/dwc3/dwc3-of-simple.c 2022-07-31 17:03:01.000000000 -0400
+++ b/drivers/usb/dwc3/dwc3-of-simple.c 2022-08-09 17:00:56.994472344 -0400
@@ -30,12 +30,16 @@
bool need_reset;
};
+struct dwc3_of_simple_data {
+ bool need_reset;
+};
+
static int dwc3_of_simple_probe(struct platform_device *pdev)
{
struct dwc3_of_simple *simple;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
-
+ const struct dwc3_of_simple_data *data = of_device_get_match_data(dev);
int ret;
simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
@@ -49,8 +53,8 @@
* Some controllers need to toggle the usb3-otg reset before trying to
* initialize the PHY, otherwise the PHY times out.
*/
- if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
- simple->need_reset = true;
+ if (data->need_reset)
+ simple->need_reset = data->need_reset;
simple->resets = of_reset_control_array_get(np, false, true,
true);
@@ -170,13 +174,34 @@
dwc3_of_simple_runtime_resume, NULL)
};
+static const struct dwc3_of_simple_data dwc3_of_simple_data_rk3399 = {
+ .need_reset = true,
+};
+
static const struct of_device_id of_dwc3_simple_match[] = {
- { .compatible = "rockchip,rk3399-dwc3" },
- { .compatible = "cavium,octeon-7130-usb-uctl" },
- { .compatible = "sprd,sc9860-dwc3" },
- { .compatible = "allwinner,sun50i-h6-dwc3" },
- { .compatible = "hisilicon,hi3670-dwc3" },
- { .compatible = "intel,keembay-dwc3" },
+ {
+ .compatible = "allwinner,sun50i-h6-dwc3",
+ },
+ {
+ .compatible = "cavium,octeon-7130-usb-uctl",
+ },
+ {
+ .compatible = "hisilicon,hi3670-dwc3",
+ },
+ {
+ .compatible = "intel,keembay-dwc3",
+ },
+ {
+ .compatible = "rockchip,rk3399-dwc3",
+ .data = &dwc3_of_simple_data_rk3399,
+ },
+ {
+ .compatible = "rockchip,rk3568-dwc3",
+ .data = &dwc3_of_simple_data_rk3399,
+ },
+ {
+ .compatible = "sprd,sc9860-dwc3",
+ },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
diff -Naur a/kernel/dma/pool.c b/kernel/dma/pool.c
--- a/kernel/dma/pool.c 2022-07-31 17:03:01.000000000 -0400
+++ b/kernel/dma/pool.c 2022-08-09 17:00:56.992472371 -0400
@@ -189,13 +189,10 @@
int ret = 0;
/*
- * If coherent_pool was not used on the command line, default the pool
- * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1.
+ * Use 2MiB as default pool size.
*/
if (!atomic_pool_size) {
- unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
- pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
- atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
+ atomic_pool_size = SZ_2M;
}
INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
diff -Naur a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
--- a/sound/soc/codecs/rt5651.c 2022-07-31 17:03:01.000000000 -0400
+++ b/sound/soc/codecs/rt5651.c 2022-08-09 17:00:56.993472358 -0400
@@ -24,6 +24,7 @@
#include <sound/initval.h>
#include <sound/tlv.h>
#include <sound/jack.h>
+#include <linux/clk.h>
#include "rl6231.h"
#include "rt5651.h"
@@ -1511,6 +1512,7 @@
static int rt5651_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
+ struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
switch (level) {
case SND_SOC_BIAS_PREPARE:
if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
@@ -1518,6 +1520,13 @@
snd_soc_component_update_bits(component, RT5651_D_MISC,
0xc00, 0xc00);
}
+ if (!IS_ERR(rt5651->mclk)){
+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
+ clk_disable_unprepare(rt5651->mclk);
+ } else {
+ clk_prepare_enable(rt5651->mclk);
+ }
+ }
break;
case SND_SOC_BIAS_STANDBY:
if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
@@ -2059,6 +2068,13 @@
{
struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
+ /* Check if MCLK provided */
+ rt5651->mclk = devm_clk_get(component->dev, "mclk");
+ if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
+ dev_err(component->dev, "unable to get mclk\n");
+ return -EPROBE_DEFER;
+ }
+
rt5651->component = component;
snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
diff -Naur a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
--- a/sound/soc/codecs/rt5651.h 2022-07-31 17:03:01.000000000 -0400
+++ b/sound/soc/codecs/rt5651.h 2022-08-09 17:00:56.994472344 -0400
@@ -2097,6 +2097,7 @@
int dmic_en;
bool hp_mute;
+ struct clk *mclk;
};
#endif /* __RT5651_H__ */
diff -Naur a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2022-07-10 17:40:51.000000000 -0400
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c 2022-07-11 05:18:34.000000000 -0400
@@ -91,80 +91,88 @@
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
- 27000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 36000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 40000000, {
- { 0x00b3, 0x0000},
- { 0x2153, 0x0000},
- { 0x40f3, 0x0000}
- },
- }, {
- 54000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
- },
- }, {
- 65000000, {
- { 0x0072, 0x0001},
- { 0x2142, 0x0001},
- { 0x40a2, 0x0001},
- },
- }, {
- 66000000, {
- { 0x013e, 0x0003},
- { 0x217e, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 74250000, {
- { 0x0072, 0x0001},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 83500000, {
- { 0x0072, 0x0001},
- },
- }, {
- 108000000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 106500000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 146250000, {
- { 0x0051, 0x0002},
- { 0x2145, 0x0002},
- { 0x4061, 0x0002}
- },
- }, {
- 148500000, {
- { 0x0051, 0x0003},
- { 0x214c, 0x0003},
- { 0x4064, 0x0003}
+ 30666000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40f3, 0x0000 },
+ },
+ }, {
+ 36800000, {
+ { 0x00b3, 0x0000 },
+ { 0x2153, 0x0000 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 46000000, {
+ { 0x00b3, 0x0000 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 61333000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x40a2, 0x0001 },
+ },
+ }, {
+ 73600000, {
+ { 0x0072, 0x0001 },
+ { 0x2142, 0x0001 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 92000000, {
+ { 0x0072, 0x0001 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 122666000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4061, 0x0002 },
+ },
+ }, {
+ 147200000, {
+ { 0x0051, 0x0002 },
+ { 0x2145, 0x0002 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 184000000, {
+ { 0x0051, 0x0002 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 226666000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x4064, 0x0003 },
+ },
+ }, {
+ 272000000, {
+ { 0x0040, 0x0003 },
+ { 0x214c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 340000000, {
+ { 0x0040, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
+ },
+ }, {
+ 600000000, {
+ { 0x1a40, 0x0003 },
+ { 0x3b4c, 0x0003 },
+ { 0x5a64, 0x0003 },
},
- }, {
+ }, {
~0UL, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
+ { 0x0000, 0x0000 },
},
}
};
@@ -172,20 +180,8 @@
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
/* pixelclk bpp8 bpp10 bpp12 */
{
- 40000000, { 0x0018, 0x0018, 0x0018 },
- }, {
- 65000000, { 0x0028, 0x0028, 0x0028 },
- }, {
- 66000000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 74250000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 83500000, { 0x0028, 0x0038, 0x0038 },
- }, {
- 146250000, { 0x0038, 0x0038, 0x0038 },
- }, {
- 148500000, { 0x0000, 0x0038, 0x0038 },
- }, {
+ 600000000, { 0x0000, 0x0000, 0x0000 },
+ }, {
~0UL, { 0x0000, 0x0000, 0x0000},
}
};
@@ -195,6 +191,7 @@
{ 74250000, 0x8009, 0x0004, 0x0272},
{ 148500000, 0x802b, 0x0004, 0x028d},
{ 297000000, 0x8039, 0x0005, 0x028d},
+ { 594000000, 0x8039, 0x0000, 0x019d},
{ ~0UL, 0x0000, 0x0000, 0x0000}
};
@@ -240,26 +237,6 @@
return 0;
}
-static enum drm_mode_status
-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
- const struct drm_display_info *info,
- const struct drm_display_mode *mode)
-{
- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
- int pclk = mode->clock * 1000;
- bool valid = false;
- int i;
-
- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
- if (pclk == mpll_cfg[i].mpixelclock) {
- valid = true;
- break;
- }
- }
-
- return (valid) ? MODE_OK : MODE_BAD;
-}
-
static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
{
}
@@ -425,7 +402,6 @@
};
static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -442,7 +418,6 @@
};
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -462,7 +437,6 @@
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -480,7 +454,6 @@
};
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -493,7 +466,6 @@
};
static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -597,6 +569,14 @@
}
if (hdmi->chip_data == &rk3568_chip_data) {
+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
+ RK3568_HDMI_SCLIN_MSK,
+ RK3568_HDMI_SDAIN_MSK |
+ RK3568_HDMI_SCLIN_MSK));
+ }
+
+ if (hdmi->chip_data == &rk3568_chip_data) {
regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
RK3568_HDMI_SCLIN_MSK,

13
patches-6.3/004-arm64-add-dts-rk3568-nanopi-r5s.patch
View File

@ -1,13 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 99a44c400..2a2176fb2 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -83,6 +83,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb

212
patches-6.3/005-friendlyelec-nanopi-series.patch
View File

@ -1,212 +0,0 @@
From e134dcd7dda9048f4ac2cab96322a8a7f08a9d22 Mon Sep 17 00:00:00 2001
From: sbwml <984419930@qq.com>
Date: Sat, 12 Nov 2022 10:24:30 +0800
Subject: [PATCH] friendlyelec-nanopi-series
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/friendlyelec/Kconfig | 11 +++
drivers/soc/friendlyelec/Makefile | 1 +
drivers/soc/friendlyelec/board.c | 143 ++++++++++++++++++++++++++++++
5 files changed, 157 insertions(+)
create mode 100644 drivers/soc/friendlyelec/Kconfig
create mode 100644 drivers/soc/friendlyelec/Makefile
create mode 100644 drivers/soc/friendlyelec/board.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index e461c0711..a65fa9f4f 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -27,5 +27,6 @@ source "drivers/soc/ti/Kconfig"
source "drivers/soc/ux500/Kconfig"
source "drivers/soc/versatile/Kconfig"
source "drivers/soc/xilinx/Kconfig"
+source "drivers/soc/friendlyelec/Kconfig"
endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 69ba6508c..16ac16900 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -33,3 +33,4 @@ obj-y += ti/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_PLAT_VERSATILE) += versatile/
obj-y += xilinx/
+obj-$(CONFIG_VENDOR_FRIENDLYELEC) += friendlyelec/
diff --git a/drivers/soc/friendlyelec/Kconfig b/drivers/soc/friendlyelec/Kconfig
new file mode 100644
index 000000000..642629ab7
--- /dev/null
+++ b/drivers/soc/friendlyelec/Kconfig
@@ -0,0 +1,11 @@
+#
+# Machine drivers
+#
+
+if ARCH_ROCKCHIP
+
+config VENDOR_FRIENDLYELEC
+ bool "FriendlyElec board based on Rockchip SoCs"
+ default n
+
+endif
diff --git a/drivers/soc/friendlyelec/Makefile b/drivers/soc/friendlyelec/Makefile
new file mode 100644
index 000000000..870542f05
--- /dev/null
+++ b/drivers/soc/friendlyelec/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_VENDOR_FRIENDLYELEC) += board.o
diff --git a/drivers/soc/friendlyelec/board.c b/drivers/soc/friendlyelec/board.c
new file mode 100644
index 000000000..886a8e1f7
--- /dev/null
+++ b/drivers/soc/friendlyelec/board.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can access it online at
+ * http://www.gnu.org/licenses/gpl-2.0.html.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/crc32.h>
+#include <linux/nvmem-consumer.h>
+
+#define BOARD_MANF "FriendlyELEC Computer Tech. Co., Ltd."
+
+static const char *board_mach;
+static const char *board_name;
+static u32 board_rev;
+static u32 board_serial_high, board_serial_low;
+
+static ssize_t board_sys_info_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ char *s = buf;
+
+ s += sprintf(s, "Hardware\t: %s\n", board_mach);
+ s += sprintf(s, "Revision\t: %04x\n", board_rev);
+ s += sprintf(s, "Serial\t\t: %08x%08x\n",
+ board_serial_high, board_serial_low);
+ s += sprintf(s, "\nModel\t\t: %s\n", board_name);
+ s += sprintf(s, "Manufacturer\t: %s\n", BOARD_MANF);
+
+ return (s - buf);
+}
+
+static struct device_attribute board_attr_info =
+ __ATTR(info, S_IRUGO, board_sys_info_show, NULL);
+
+static int rockchip_cpuinfo_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct nvmem_cell *cell;
+ unsigned char *efuse_buf, buf[16];
+ size_t len;
+ int i;
+
+ cell = nvmem_cell_get(dev, "id");
+ if (IS_ERR(cell)) {
+ dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
+ return PTR_ERR(cell);
+ }
+
+ efuse_buf = nvmem_cell_read(cell, &len);
+ nvmem_cell_put(cell);
+
+ if (len != 16) {
+ kfree(efuse_buf);
+ dev_err(dev, "invalid id len: %zu\n", len);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < 8; i++) {
+ buf[i] = efuse_buf[1 + (i << 1)];
+ buf[i + 8] = efuse_buf[i << 1];
+ }
+
+ kfree(efuse_buf);
+
+ board_serial_low = crc32(0, buf, 8);
+ board_serial_high = crc32(board_serial_low, buf + 8, 8);
+
+ dev_info(dev, "Serial\t\t: %08x%08x\n",
+ board_serial_high, board_serial_low);
+
+ return 0;
+}
+
+static int board_sys_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *root;
+
+ root = of_find_node_by_path("/");
+
+ of_property_read_u32(np, "hwrev", &board_rev);
+
+ if (of_property_read_string(np, "machine", &board_mach))
+ of_property_read_string(root, "compatible", &board_mach);
+
+ if (of_property_read_string(np, "model", &board_name))
+ of_property_read_string(root, "model", &board_name);
+
+ of_node_put(root);
+
+ rockchip_cpuinfo_probe(pdev);
+
+ device_create_file(&pdev->dev, &board_attr_info);
+
+ return 0;
+}
+
+static const struct of_device_id board_sys_of_match[] = {
+ { .compatible = "friendlyelec,board" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, board_sys_of_match);
+
+static struct platform_driver board_sys_driver = {
+ .probe = board_sys_probe,
+ .driver = {
+ .name = "friendlyelec-board",
+ .of_match_table = board_sys_of_match,
+ },
+};
+
+static int __init board_sys_init(void)
+{
+ return platform_driver_register(&board_sys_driver);
+}
+late_initcall(board_sys_init);
+
+MODULE_AUTHOR("support@friendlyarm.com");
+MODULE_DESCRIPTION("FriendlyElec NanoPi Series Machine Driver");
+MODULE_LICENSE("GPL v2");
--
2.34.1

92
patches-6.3/007-rockchip-p3phy-fw.patch
View File

@ -1,92 +0,0 @@
From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Mon, 11 Jul 2022 20:35:52 +0800
Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
This fw fix some RX issue:
1. connect detect error;
2. transfer error in ssd huge data write(more than 10GB).
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
---
drivers/phy/phy-rockchip-snps-pcie3.c | 36 +-
drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
2 files changed, 8225 insertions(+), 3 deletions(-)
create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -20,6 +20,7 @@
/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON4 0x10
#define GRF_PCIE30PHY_CON6 0x18
#define GRF_PCIE30PHY_CON9 0x24
#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops {
int (*phy_init)(struct rockchip_p3phy_priv *priv);
};
+static u16 phy_fw[] = {
+ #include "p3phy.fw"
+};
+
static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
@@ -87,13 +92,14 @@ static int rockchip_p3phy_rk3568_init(st
{
struct phy *phy = priv->phy;
bool bifurcation = false;
+ int i;
int ret;
u32 reg;
/* Deassert PCIe PMA output clamp mode */
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
- for (int i = 0; i < priv->num_lanes; i++) {
+ for (i = 0; i < priv->num_lanes; i++) {
dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
if (priv->lanes[i] > 1)
bifurcation = true;
@@ -112,16 +118,35 @@ static int rockchip_p3phy_rk3568_init(st
GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
}
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
+
reset_control_deassert(priv->p30phy);
ret = regmap_read_poll_timeout(priv->phy_grf,
GRF_PCIE30PHY_STATUS0,
reg, SRAM_INIT_DONE(reg),
0, 500);
- if (ret)
+ if (ret) {
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
__func__, reg);
- return ret;
+ return ret;
+ }
+
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
+ for (i = 0; i < 8192; i++)
+ writel(phy_fw[i], priv->mmio + (i<<2));
+
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+ (0x0 << 8) | (0x3 << (8 + 16)));
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+
+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
+ return 0;
}
static const struct rockchip_p3phy_ops rk3568_ops = {

20
patches-6.3/008-r4s-add-eeprom.patch
View File

@ -1,20 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index fe5b52610..993d85f47 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -68,6 +68,15 @@ &emmc_phy {
status = "disabled";
};
+&i2c2 {
+ eeprom@51 {
+ compatible = "microchip,24c02", "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ read-only; /* This holds our MAC */
+ };
+};
+
&i2c4 {
status = "disabled";
};

18
patches-6.3/009-r4s-add-led-action-for-openwrt.patch
View File

@ -1,18 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index 993d85f47..15feab9a4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -19,6 +19,13 @@ / {
model = "FriendlyElec NanoPi R4S";
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+ aliases {
+ led-boot = &sys_led;
+ led-failsafe = &sys_led;
+ led-running = &sys_led;
+ led-upgrade = &sys_led;
+ };
+
/delete-node/ display-subsystem;
gpio-leds {

16
patches-6.3/010-r4s-sd-signalling.patch
View File

@ -1,16 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index 15feab9a4..038d17276 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -128,6 +128,11 @@ &sdio0 {
status = "disabled";
};
+&sdmmc {
+ /delete-property/ sd-uhs-sdr104;
+ cap-sd-highspeed;
+};
+
&u2phy0_host {
phy-supply = <&vdd_5v>;
};

24
patches-6.3/011-r4s-add-OF-node-for-pcie-eth.patch
View File

@ -1,24 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
index 038d17276..16d2d8cc2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -92,6 +92,19 @@ &pcie0 {
max-link-speed = <1>;
num-lanes = <1>;
vpcie3v3-supply = <&vcc3v3_sys>;
+
+ pcie@0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@0,0 {
+ compatible = "pci10ec,8168";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x870>;
+ };
+ };
};
&pinctrl {

165
patches-6.3/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch
View File

@ -1,165 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index cc4848914..5262580ae 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -297,6 +297,7 @@ usb_host0_xhci: usb@fcc00000 {
power-domains = <&power RK3568_PD_PIPE>;
resets = <&cru SRST_USB3OTG0>;
snps,dis_u2_susphy_quirk;
+ snps,xhci-trb-ent-quirk;
status = "disabled";
};
@@ -315,6 +316,7 @@ usb_host1_xhci: usb@fd000000 {
power-domains = <&power RK3568_PD_PIPE>;
resets = <&cru SRST_USB3OTG1>;
snps,dis_u2_susphy_quirk;
+ snps,xhci-trb-ent-quirk;
status = "disabled";
};
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 476b63618..2241fcc31 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1551,6 +1551,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,dis-del-phy-power-chg-quirk");
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
"snps,dis-tx-ipgap-linecheck-quirk");
+ dwc->xhci_trb_ent_quirk = device_property_read_bool(dev,
+ "snps,xhci-trb-ent-quirk");
dwc->resume_hs_terminations = device_property_read_bool(dev,
"snps,resume-hs-terminations");
dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4743e918d..c9e6d27c9 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1098,6 +1098,9 @@ struct dwc3_scratchpad_array {
* change quirk.
* @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
* check during HS transmit.
+ * @xhci_trb_ent_quirk: set if need to enable the Evaluate Next TRB(ENT)
+ * flag in the TRB data structure to force xHC to
+ * pre-fetch the next TRB of a TD.
* @resume_hs_terminations: Set if we enable quirk for fixing improper crc
* generation after resume from suspend.
* @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
@@ -1316,6 +1319,7 @@ struct dwc3 {
unsigned dis_u2_freeclk_exists_quirk:1;
unsigned dis_del_phy_power_chg_quirk:1;
unsigned dis_tx_ipgap_linecheck_quirk:1;
+ unsigned xhci_trb_ent_quirk:1;
unsigned resume_hs_terminations:1;
unsigned parkmode_disable_ss_quirk:1;
unsigned gfladj_refclk_lpm_sel:1;
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index f6f13e7f1..08a528693 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -66,7 +66,7 @@ static int dwc3_host_get_irq(struct dwc3 *dwc)
int dwc3_host_init(struct dwc3 *dwc)
{
- struct property_entry props[4];
+ struct property_entry props[5];
struct platform_device *xhci;
int ret, irq;
int prop_idx = 0;
@@ -97,6 +97,9 @@ int dwc3_host_init(struct dwc3 *dwc)
if (dwc->usb3_lpm_capable)
props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");
+ if (dwc->xhci_trb_ent_quirk)
+ props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-trb-ent-quirk");
+
if (dwc->usb2_lpm_disable)
props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb2-lpm-disable");
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 5fb55bf19..44e3c87d2 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -301,6 +301,9 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (device_property_read_bool(tmpdev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
+ if (device_property_read_bool(tmpdev, "xhci-trb-ent-quirk"))
+ xhci->quirks |= XHCI_TRB_ENT_QUIRK;
+
device_property_read_u32(tmpdev, "imod-interval-ns",
&xhci->imod_interval);
}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 343709af4..785e5263f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -3526,6 +3526,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
bool more_trbs_coming = true;
bool need_zero_pkt = false;
bool first_trb = true;
+ bool en_trb_ent = true;
unsigned int num_trbs;
unsigned int start_cycle, num_sgs = 0;
unsigned int enqd_len, block_len, trb_buff_len, full_len;
@@ -3562,6 +3563,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
need_zero_pkt = true;
+ /*
+ * Don't enable the ENT flag in the TRB if
+ * the EP support bulk streaming protocol.
+ */
+ if (urb->stream_id)
+ en_trb_ent = false;
+
td = &urb_priv->td[0];
/*
@@ -3590,6 +3598,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
first_trb = false;
if (start_cycle == 0)
field |= TRB_CYCLE;
+ /*
+ * Don't enable the ENT flag in the TRB if the
+ * transfer length of the first TRB isn't an
+ * integer multiple of the EP maxpacket.
+ */
+ if (trb_buff_len % usb_endpoint_maxp(&urb->ep->desc))
+ en_trb_ent = false;
} else
field |= ring->cycle_state;
@@ -3598,6 +3613,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
*/
if (enqd_len + trb_buff_len < full_len) {
field |= TRB_CHAIN;
+ if (xhci->quirks & XHCI_TRB_ENT_QUIRK && en_trb_ent)
+ field |= TRB_ENT;
if (trb_is_link(ring->enqueue + 1)) {
if (xhci_align_td(xhci, urb, enqd_len,
&trb_buff_len,
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index c9f06c5e4..e57460e21 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1525,7 +1525,11 @@ static inline const char *xhci_trb_type_string(u8 type)
#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
/* TRB buffer pointers can't cross 64KB boundaries */
+#ifdef CONFIG_ARCH_ROCKCHIP
+#define TRB_MAX_BUFF_SHIFT 12
+#else
#define TRB_MAX_BUFF_SHIFT 16
+#endif
#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
/* How much data is left before the 64KB boundary? */
#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
@@ -1842,6 +1846,7 @@ struct xhci_hcd {
#define XHCI_STATE_HALTED (1 << 1)
#define XHCI_STATE_REMOVING (1 << 2)
unsigned long long quirks;
+#define XHCI_TRB_ENT_QUIRK BIT_ULL(63)
#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
#define XHCI_NEC_HOST BIT_ULL(2)

20
patches-6.3/013-rk3399-add-dwc3-xhci-usb-trb-quirk.patch
View File

@ -1,20 +0,0 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 59858f2dc8b9..2b8f11aebf13 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -459,6 +459,7 @@ usbdrd_dwc3_0: usb@fe800000 {
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
+ snps,xhci-trb-ent-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
power-domains = <&power RK3399_PD_USB3>;
@@ -495,6 +496,7 @@ usbdrd_dwc3_1: usb@fe900000 {
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
+ snps,xhci-trb-ent-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
power-domains = <&power RK3399_PD_USB3>;

35
patches-6.3/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
View File

@ -1,35 +0,0 @@
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Wed, 20 Feb 2019 07:38:34 +0000
Subject: [PATCH] mmc: core: set initial signal voltage on power off
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. If the card has not been power cycled, it may still be
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
will fail to boot from a UHS card that continue to use 1.8V signaling.
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
same issue have been seen on some Rockchip RK3399 boards.
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
this change fix a re-boot issue on my boards and does not break emmc/sdio.
Is this an acceptable workaround? Any advice is appreciated.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/mmc/core/core.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -1366,6 +1366,8 @@ void mmc_power_off(struct mmc_host *host
mmc_pwrseq_power_off(host);
+ mmc_set_initial_signal_voltage(host);
+
host->ios.clock = 0;
host->ios.vdd = 0;

40
patches-6.3/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch
View File

@ -1,40 +0,0 @@
From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
From: Andrew Powers-Holmes <aholmes@omnom.net>
Date: Sat, 12 Nov 2022 22:41:26 +1100
Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
range mappings
The register and range mappings for the PCIe controller in Rockchip's
RK356x SoCs are incorrect. Replace them with corrected values from the
vendor BSP sources, updated to match current DT schema.
Tested-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
---
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
2 files changed, 12 insertions(+), 9 deletions(-)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 {
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
<0x0 0xfe260000 0x0 0x00010000>,
- <0x3 0x3f000000 0x0 0x01000000>;
+ <0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 {
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;

94
patches-6.3/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
View File

@ -1,94 +0,0 @@
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1133,6 +1133,14 @@ config SOCIONEXT_SYNQUACER_PREITS
If unsure, say Y.
+config ROCKCHIP_ERRATUM_114514
+ bool "Rockchip RK3568 force no_local_cache"
+ default y
+ help
+ They consider this as a SoC implement design instead of a bug.
+
+ If unsure, say Y.
+
endmenu # "ARM errata workarounds via the alternatives framework"
choice
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -64,7 +64,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x10 0x1f>;
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
<&cru CLK_PCIE30X1_AUX_NDFT>;
@@ -87,7 +87,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x1000 0x1000>;
+ msi-map = <0x1000 &its 0x1000 0x1000>;
num-lanes = <1>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
@@ -116,7 +116,7 @@
compatible = "rockchip,rk3568-pcie";
#address-cells = <3>;
#size-cells = <2>;
- bus-range = <0x0 0xf>;
+ bus-range = <0x20 0x2f>;
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>;
@@ -139,7 +139,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <3>;
- msi-map = <0x0 &gic 0x2000 0x1000>;
+ msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -315,14 +315,21 @@
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
- <0x0 0xfd460000 0 0x80000>; /* GICR */
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd410000>;
- mbi-ranges = <296 24>;
- msi-controller;
+ its: interrupt-controller@fd440000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0xfd440000 0x0 0x20000>;
+ };
};
usb_host0_ehci: usb@fd800000 {
@@ -975,7 +982,7 @@
num-ib-windows = <6>;
num-ob-windows = <2>;
max-link-speed = <2>;
- msi-map = <0x0 &gic 0x0 0x1000>;
+ msi-map = <0x0 &its 0x0 0x1000>;
num-lanes = <1>;
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";

198
patches-6.3/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
View File

@ -1,198 +0,0 @@
From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001
From: Peter Geis <pgwipeout@gmail.com>
Date: Thu, 3 Jun 2021 11:36:35 -0400
Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
---
drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
1 file changed, 65 insertions(+), 5 deletions(-)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -45,6 +45,7 @@
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE (1 << 2)
#define RD_LOCAL_LPI_ENABLED BIT(0)
#define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
@@ -2172,6 +2173,11 @@ static struct page *its_allocate_prop_table(gfp_t gfp_flags)
{
struct page *prop_page;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+ pr_err("ITS ALLOCATE PROP WORKAROUND\n");
+ gfp_flags |= GFP_DMA;
+ }
+
prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
if (!prop_page)
return NULL;
@@ -2295,6 +2301,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
u32 alloc_pages, psz;
struct page *page;
void *base;
+ gfp_t gfp_flags;
psz = baser->psz;
alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
@@ -2306,7 +2313,10 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
order = get_order(GITS_BASER_PAGES_MAX * psz);
}
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+ gfp_flags |= GFP_DMA;
+ page = alloc_pages_node(its->numa_node, gfp_flags, order);
if (!page)
return -ENOMEM;
@@ -2353,6 +2363,13 @@ retry_baser:
its_write_baser(its, baser, val);
tmp = baser->val;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ else
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
+ }
+
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
/*
* Shareability didn't stick. Just use
@@ -2935,6 +2952,10 @@ static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
struct page *pend_page;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+ gfp_flags |= GFP_DMA;
+ }
+
pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
get_order(LPI_PENDBASE_SZ));
if (!pend_page)
@@ -3092,6 +3113,9 @@ static void its_cpu_init_lpis(void)
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
/*
@@ -3116,6 +3140,9 @@ static void its_cpu_init_lpis(void)
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
/*
* The HW reports non-shareable, we must remove the
@@ -3278,7 +3305,12 @@ static bool its_alloc_table_entry(struct its_node *its,
/* Allocate memory for 2nd level table */
if (!table[idx]) {
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+ gfp_flags |= GFP_DMA;
+ }
+
+ page = alloc_pages_node(its->numa_node, gfp_flags,
get_order(baser->psz));
if (!page)
return false;
@@ -3367,6 +3399,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
int nr_lpis;
int nr_ites;
int sz;
+ gfp_t gfp_flags;
if (!its_alloc_device_table(its, dev_id))
return NULL;
@@ -3374,7 +3407,11 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
if (WARN_ON(!is_power_of_2(nvecs)))
nvecs = roundup_pow_of_two(nvecs);
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ gfp_flags = GFP_KERNEL;
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+ gfp_flags |= GFP_DMA;
+
+ dev = kzalloc(sizeof(*dev), gfp_flags);
/*
* Even if the device wants a single LPI, the ITT must be
* sized as a power of two (and you need at least one bit...).
@@ -3382,7 +3419,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
nr_ites = max(2, nvecs);
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
+ itt = kzalloc_node(sz, gfp_flags, its->numa_node);
if (alloc_lpis) {
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
if (lpi_map)
@@ -4705,6 +4742,13 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
return true;
}
+static bool __maybe_unused its_enable_quirk_rk3568(void *data)
+{
+ gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
+
+ return true;
+}
+
static const struct gic_quirk its_quirks[] = {
#ifdef CONFIG_CAVIUM_ERRATUM_22375
{
@@ -4750,6 +4794,14 @@ static const struct gic_quirk its_quirks[] = {
.mask = 0xffffffff,
.init = its_enable_quirk_hip07_161600802,
},
+#endif
+#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
+ {
+ .desc = "ITS: Rockchip erratum 114514",
+ .iidr = 0x0201743b,
+ .mask = 0xffffffff,
+ .init = its_enable_quirk_rk3568,
+ },
#endif
{
}
@@ -4974,6 +5026,7 @@ static int __init its_probe_one(struct resource *res,
struct page *page;
u32 ctlr;
int err;
+ gfp_t gfp_flags;
its_base = its_map_one(res, &err);
if (!its_base)
@@ -5042,7 +5095,9 @@ static int __init its_probe_one(struct resource *res,
its->numa_node = numa_node;
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+ gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
+
+ page = alloc_pages_node(its->numa_node, gfp_flags,
get_order(ITS_CMD_QUEUE_SZ));
if (!page) {
err = -ENOMEM;
@@ -5073,6 +5128,9 @@ static int __init its_probe_one(struct resource *res,
gits_write_cbaser(baser, its->base + GITS_CBASER);
tmp = gits_read_cbaser(its->base + GITS_CBASER);
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
/*

402
patches-6.3/220-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
View File

@ -1,402 +0,0 @@
From d591c3f6efef5f50fc970aeeedbf9e03b7bd5d21 Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 17 Jun 2022 10:38:30 +0800
Subject: [PATCH] PCI: Add ROCKCHIP PCIe ASPM interface
Change-Id: I1156bd10e352145d745899067bf43afda92d5a30
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/pci/pcie/Kconfig | 6 +
drivers/pci/pcie/Makefile | 1 +
drivers/pci/pcie/aspm_ext.c | 339 ++++++++++++++++++++++++++++++++++++
include/linux/aspm_ext.h | 16 ++
4 files changed, 362 insertions(+)
create mode 100644 drivers/pci/pcie/aspm_ext.c
create mode 100644 include/linux/aspm_ext.h
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -114,6 +114,12 @@ config PCIEASPM_PERFORMANCE
Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
endchoice
+config PCIEASPM_EXT
+ tristate "Extend ASPM function"
+ depends on PCIEASPM
+ help
+ This enables the extensions APIs for ASPM control.
+
config PCIE_PME
def_bool y
depends on PCIEPORTBUS && PM
--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
@@ -7,6 +7,7 @@ pcieportdrv-y := portdrv.o rcec.o
obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
obj-$(CONFIG_PCIEASPM) += aspm.o
+obj-$(CONFIG_PCIEASPM_EXT) += aspm_ext.o
obj-$(CONFIG_PCIEAER) += aer.o err.o
obj-$(CONFIG_PCIEAER_INJECT) += aer_inject.o
obj-$(CONFIG_PCIE_PME) += pme.o
--- /dev/null
+++ b/drivers/pci/pcie/aspm_ext.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip PCIe Apis For WIFI
+ *
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/aspm_ext.h>
+#include <linux/errno.h>
+
+
+static u32 rockchip_pcie_pcie_access_cap(struct pci_dev *pdev, int cap, uint offset,
+ bool is_ext, bool is_write, u32 writeval)
+{
+ int cap_ptr = 0;
+ u32 ret = -1;
+ u32 readval;
+
+ if (!(pdev)) {
+ pci_err(pdev, "%s: pdev is NULL\n", __func__);
+ return ret;
+ }
+
+ /* Find Capability offset */
+ if (is_ext) {
+ /* removing max EXT_CAP_ID check as
+ * linux kernel definition's max value is not updated yet as per spec
+ */
+ cap_ptr = pci_find_ext_capability(pdev, cap);
+
+ } else {
+ /* removing max PCI_CAP_ID_MAX check as
+ * previous kernel versions dont have this definition
+ */
+ cap_ptr = pci_find_capability(pdev, cap);
+ }
+
+ /* Return if capability with given ID not found */
+ if (cap_ptr == 0) {
+ pci_err(pdev, "%s: PCI Cap(0x%02x) not supported.\n",
+ __func__, cap);
+ return -EINVAL;
+ }
+
+ if (is_write) {
+ pci_write_config_dword(pdev, (cap_ptr + offset), writeval);
+ ret = 0;
+
+ } else {
+ pci_read_config_dword(pdev, (cap_ptr + offset), &readval);
+ ret = readval;
+ }
+
+ return ret;
+}
+
+static bool rockchip_pcie_bus_aspm_enable_dev(char *device, struct pci_dev *dev, bool enable)
+{
+ u32 linkctrl_before;
+ u32 linkctrl_after = 0;
+ u8 linkctrl_asm;
+
+ linkctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
+ false, false, 0);
+ linkctrl_asm = (linkctrl_before & PCI_EXP_LNKCTL_ASPMC);
+
+ if (enable) {
+ if (linkctrl_asm == PCI_EXP_LNKCTL_ASPM_L1) {
+ pci_err(dev, "%s: %s already enabled linkctrl: 0x%x\n",
+ __func__, device, linkctrl_before);
+ return false;
+ }
+ /* Enable only L1 ASPM (bit 1) */
+ rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
+ true, (linkctrl_before | PCI_EXP_LNKCTL_ASPM_L1));
+ } else {
+ if (linkctrl_asm == 0) {
+ pci_err(dev, "%s: %s already disabled linkctrl: 0x%x\n",
+ __func__, device, linkctrl_before);
+ return false;
+ }
+ /* Disable complete ASPM (bit 1 and bit 0) */
+ rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
+ true, (linkctrl_before & (~PCI_EXP_LNKCTL_ASPMC)));
+ }
+
+ linkctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
+ false, false, 0);
+ pci_err(dev, "%s: %s %s, linkctrl_before: 0x%x linkctrl_after: 0x%x\n",
+ __func__, device, (enable ? "ENABLE " : "DISABLE"),
+ linkctrl_before, linkctrl_after);
+
+ return true;
+}
+
+bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
+{
+ bool ret;
+
+ if (enable) {
+ /* Enable only L1 ASPM first RC then EP */
+ ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
+ ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
+ } else {
+ /* Disable complete ASPM first EP then RC */
+ ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
+ ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
+ }
+
+ return ret;
+}
+
+static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
+ u32 clear, u32 set)
+{
+ u32 val;
+
+ pci_read_config_dword(pdev, pos, &val);
+ val &= ~clear;
+ val |= set;
+ pci_write_config_dword(pdev, pos, val);
+}
+
+/* Convert L1SS T_pwr encoding to usec */
+static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
+{
+ switch (scale) {
+ case 0:
+ return val * 2;
+ case 1:
+ return val * 10;
+ case 2:
+ return val * 100;
+ }
+
+ return 0;
+}
+
+static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
+{
+ u32 threshold_ns = threshold_us * 1000;
+
+ /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
+ if (threshold_ns < 32) {
+ *scale = 0;
+ *value = threshold_ns;
+ } else if (threshold_ns < 1024) {
+ *scale = 1;
+ *value = threshold_ns >> 5;
+ } else if (threshold_ns < 32768) {
+ *scale = 2;
+ *value = threshold_ns >> 10;
+ } else if (threshold_ns < 1048576) {
+ *scale = 3;
+ *value = threshold_ns >> 15;
+ } else if (threshold_ns < 33554432) {
+ *scale = 4;
+ *value = threshold_ns >> 20;
+ } else {
+ *scale = 5;
+ *value = threshold_ns >> 25;
+ }
+}
+
+/* Calculate L1.2 PM substate timing parameters */
+static void aspm_calc_l1ss_info(struct pci_dev *child, struct pci_dev *parent)
+{
+ u32 val1, val2, scale1, scale2;
+ u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
+ u32 ctl1 = 0, ctl2 = 0;
+ u32 pctl1, pctl2, cctl1, cctl2;
+ u32 pl1_2_enables, cl1_2_enables;
+ u32 parent_l1ss_cap, child_l1ss_cap;
+
+ /* Setup L1 substate */
+ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
+ &parent_l1ss_cap);
+ pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
+ &child_l1ss_cap);
+
+ /* Choose the greater of the two Port Common_Mode_Restore_Times */
+ val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+ val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+ t_common_mode = max(val1, val2);
+
+ /* Choose the greater of the two Port T_POWER_ON times */
+ val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+ scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+ val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+ scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+
+ if (calc_l1ss_pwron(parent, scale1, val1) >
+ calc_l1ss_pwron(child, scale2, val2)) {
+ ctl2 |= scale1 | (val1 << 3);
+ t_power_on = calc_l1ss_pwron(parent, scale1, val1);
+ } else {
+ ctl2 |= scale2 | (val2 << 3);
+ t_power_on = calc_l1ss_pwron(child, scale2, val2);
+ }
+
+ /* Set LTR_L1.2_THRESHOLD to the time required to transition the
+ * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
+ * downstream devices report (via LTR) that they can tolerate at
+ * least that much latency.
+ *
+ * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
+ * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
+ * least 4us.
+ */
+ l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
+ encode_l12_threshold(l1_2_threshold, &scale, &value);
+ ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
+
+ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
+ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
+ pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
+ pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
+
+ if (ctl1 == pctl1 && ctl1 == cctl1 &&
+ ctl2 == pctl2 && ctl2 == cctl2)
+ return;
+
+ /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
+ pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+ cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+
+ if (pl1_2_enables || cl1_2_enables) {
+ pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_L1_2_MASK, 0);
+ pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_L1_2_MASK, 0);
+ }
+
+ /* Program T_POWER_ON times in both ports */
+ pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
+ pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
+
+ /* Program Common_Mode_Restore_Time in upstream device */
+ pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
+
+ /* Program LTR_L1.2_THRESHOLD time in both ports */
+ pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+ PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
+ pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
+ PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+ PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
+
+ if (pl1_2_enables || cl1_2_enables) {
+ pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
+ pl1_2_enables);
+ pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
+ cl1_2_enables);
+ }
+}
+
+static void rockchip_pcie_bus_l1ss_enable_dev(char *device, struct pci_dev *dev, bool enable)
+{
+ u32 l1ssctrl_before;
+ u32 l1ssctrl_after = 0;
+ u8 l1ss_ep;
+
+ /* Extendend Capacility Reg */
+ l1ssctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
+ PCI_L1SS_CTL1, true, false, 0);
+ l1ss_ep = (l1ssctrl_before & PCI_L1SS_CTL1_L1SS_MASK);
+
+ if (enable) {
+ if (l1ss_ep == PCI_L1SS_CTL1_L1SS_MASK) {
+ pci_err(dev, "%s: %s already enabled, l1ssctrl: 0x%x\n",
+ __func__, device, l1ssctrl_before);
+ return;
+ }
+ rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
+ true, true, (l1ssctrl_before | PCI_L1SS_CTL1_L1SS_MASK));
+ } else {
+ if (l1ss_ep == 0) {
+ pci_err(dev, "%s: %s already disabled, l1ssctrl: 0x%x\n",
+ __func__, device, l1ssctrl_before);
+ return;
+ }
+ rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
+ true, true, (l1ssctrl_before & (~PCI_L1SS_CTL1_L1SS_MASK)));
+ }
+ l1ssctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
+ PCI_L1SS_CTL1, true, false, 0);
+ pci_err(dev, "%s: %s %s, l1ssctrl_before: 0x%x l1ssctrl_after: 0x%x\n",
+ __func__, device, (enable ? "ENABLE " : "DISABLE"),
+ l1ssctrl_before, l1ssctrl_after);
+}
+
+bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent)
+{
+ u32 parent_l1ss_cap, child_l1ss_cap;
+
+ /* Setup L1 substate */
+ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
+ &parent_l1ss_cap);
+ pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
+ &child_l1ss_cap);
+
+ if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
+ parent_l1ss_cap = 0;
+ if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
+ child_l1ss_cap = 0;
+
+ if (parent_l1ss_cap && child_l1ss_cap)
+ return true;
+ else
+ return false;
+}
+EXPORT_SYMBOL(pcie_aspm_ext_is_rc_ep_l1ss_capable);
+
+void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable)
+{
+ bool ret;
+
+ /* Disable ASPM of RC and EP */
+ ret = rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, false);
+
+ if (enable) {
+ /* Enable RC then EP */
+ aspm_calc_l1ss_info(child, parent);
+ rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
+ rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
+ } else {
+ /* Disable EP then RC */
+ rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
+ rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
+ }
+
+ /* Enable ASPM of RC and EP only if this API disabled */
+ if (ret)
+ rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, true);
+}
+EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable);
--- /dev/null
+++ b/include/linux/aspm_ext.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */
+
+#ifndef _ASPM_EXT_H
+#define _ASPM_EXT_H
+
+#if IS_REACHABLE(CONFIG_PCIEASPM_EXT)
+bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent);
+void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable);
+#else
+static inline bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent) { return false; }
+static inline void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable) {}
+#endif
+
+#endif

24
patches-6.3/221-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
View File

@ -1,24 +0,0 @@
From a6c71606de486944c5fb028f47604fb22292312b Mon Sep 17 00:00:00 2001
From: Jon Lin <jon.lin@rock-chips.com>
Date: Fri, 24 Jun 2022 21:32:11 +0800
Subject: [PATCH] PCI: aspm_ext: Re-enable LRT for L1SS after power loss
Change-Id: Iedb72ee74660a8f11f38895e06766c3b77728ba3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
drivers/pci/pcie/aspm_ext.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/pci/pcie/aspm_ext.c
+++ b/drivers/pci/pcie/aspm_ext.c
@@ -322,6 +322,10 @@ void pcie_aspm_ext_l1ss_enable(struct pc
ret = rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, false);
if (enable) {
+ /* LRT enable bits loss after wifi off, enable it after power on */
+ if (parent->ltr_path)
+ pcie_capability_set_word(parent, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
+
/* Enable RC then EP */
aspm_calc_l1ss_info(child, parent);
rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);

38
patches-6.3/222-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
View File

@ -1,38 +0,0 @@
From cf03561e5ec9f2f8b41a992f3b8ca19b9c3b9e47 Mon Sep 17 00:00:00 2001
From: Tao Huang <huangtao@rock-chips.com>
Date: Fri, 15 Jul 2022 20:56:15 +0800
Subject: [PATCH] PCI: aspm_ext: Fix Add missing MODULE_LICENSE()
ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/pcie/aspm_ext.o
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Id365aba7a73f02cc2c61882b46937250e64af01c
---
drivers/pci/pcie/aspm_ext.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/pci/pcie/aspm_ext.c
+++ b/drivers/pci/pcie/aspm_ext.c
@@ -6,6 +6,7 @@
*/
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/pci.h>
#include <linux/aspm_ext.h>
#include <linux/errno.h>
@@ -95,7 +96,7 @@ static bool rockchip_pcie_bus_aspm_enabl
return true;
}
-bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
+static bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
{
bool ret;
@@ -341,3 +342,5 @@ void pcie_aspm_ext_l1ss_enable(struct pc
rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, true);
}
EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable);
+
+MODULE_LICENSE("GPL");

662
patches-6.3/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch
View File

@ -1,662 +0,0 @@
From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Tue, 19 Nov 2019 12:49:48 +0800
Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
Signed-off-by: hmz007 <hmz007@gmail.com>
---
drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
1 file changed, 505 insertions(+), 49 deletions(-)
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -18,25 +18,66 @@
#include <linux/list.h>
#include <linux/of.h>
-#include <soc/rockchip/rk3399_grf.h>
-
-#define RK3399_DMC_NUM_CH 2
+#define PX30_PMUGRF_OS_REG2 0x208
+#define RK3128_GRF_SOC_CON0 0x140
+#define RK3128_GRF_OS_REG1 0x1cc
+#define RK3128_GRF_DFI_WRNUM 0x220
+#define RK3128_GRF_DFI_RDNUM 0x224
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
+
+#define RK3288_PMU_SYS_REG2 0x9c
+#define RK3288_GRF_SOC_CON4 0x254
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
+#define RK3288_DFI_EN (0x30003 << 14)
+#define RK3288_DFI_DIS (0x30000 << 14)
+#define RK3288_LPDDR_SEL (0x10001 << 13)
+#define RK3288_DDR3_SEL (0x10000 << 13)
+
+#define RK3328_GRF_OS_REG2 0x5d0
+
+#define RK3368_GRF_DDRC0_CON0 0x600
+#define RK3368_GRF_SOC_STATUS5 0x494
+#define RK3368_GRF_SOC_STATUS6 0x498
+#define RK3368_GRF_SOC_STATUS8 0x4a0
+#define RK3368_GRF_SOC_STATUS9 0x4a4
+#define RK3368_GRF_SOC_STATUS10 0x4a8
+#define RK3368_DFI_EN (0x30003 << 5)
+#define RK3368_DFI_DIS (0x30000 << 5)
+
+#define MAX_DMC_NUM_CH 2
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
/* DDRMON_CTRL */
-#define DDRMON_CTRL 0x04
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
-#define LPDDR4_EN (0x10001 << 4)
-#define HARDWARE_EN (0x10001 << 3)
-#define LPDDR3_EN (0x10001 << 2)
-#define SOFTWARE_EN (0x10001 << 1)
-#define SOFTWARE_DIS (0x10000 << 1)
-#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CTRL 0x04
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
+#define DDR4_EN (0x10001 << 5)
+#define LPDDR4_EN (0x10001 << 4)
+#define HARDWARE_EN (0x10001 << 3)
+#define LPDDR2_3_EN (0x10001 << 2)
+#define SOFTWARE_EN (0x10001 << 1)
+#define SOFTWARE_DIS (0x10000 << 1)
+#define TIME_CNT_EN (0x10001 << 0)
#define DDRMON_CH0_COUNT_NUM 0x28
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
#define DDRMON_CH1_COUNT_NUM 0x3c
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/* pmu grf */
+#define PMUGRF_OS_REG2 0x308
+
+enum {
+ DDR4 = 0,
+ DDR3 = 3,
+ LPDDR2 = 5,
+ LPDDR3 = 6,
+ LPDDR4 = 7,
+ UNUSED = 0xFF
+};
+
struct dmc_usage {
u32 access;
u32 total;
@@ -50,33 +91,261 @@ struct dmc_usage {
struct rockchip_dfi {
struct devfreq_event_dev *edev;
struct devfreq_event_desc *desc;
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
struct device *dev;
void __iomem *regs;
struct regmap *regmap_pmu;
+ struct regmap *regmap_grf;
+ struct regmap *regmap_pmugrf;
struct clk *clk;
+ u32 dram_type;
+ /*
+ * available mask, 1: available, 0: not available
+ * each bit represent a channel
+ */
+ u32 ch_msk;
+};
+
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf,
+ RK3128_GRF_SOC_CON0,
+ RK3128_DDR_MONITOR_EN);
+}
+
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf,
+ RK3128_GRF_SOC_CON0,
+ RK3128_DDR_MONITOR_DISB);
+}
+
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3128_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3128_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ unsigned long flags;
+ u32 dfi_wr, dfi_rd, dfi_timer;
+
+ local_irq_save(flags);
+
+ rk3128_dfi_stop_hardware_counter(edev);
+
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
+
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
+ edata->total_count = dfi_timer;
+
+ rk3128_dfi_start_hardware_counter(edev);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3128_dfi_ops = {
+ .disable = rk3128_dfi_disable,
+ .enable = rk3128_dfi_enable,
+ .get_event = rk3128_dfi_get_event,
+ .set_event = rk3128_dfi_set_event,
+};
+
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
+}
+
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
+}
+
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3288_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3288_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ u32 tmp, max = 0;
+ u32 i, busier_ch = 0;
+ u32 rd_count, wr_count, total_count;
+
+ rk3288_dfi_stop_hardware_counter(edev);
+
+ /* Find out which channel is busier */
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
+ if (!(info->ch_msk & BIT(i)))
+ continue;
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
+ regmap_read(info->regmap_grf,
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
+ info->ch_usage[i].total = total_count;
+ tmp = info->ch_usage[i].access;
+ if (tmp > max) {
+ busier_ch = i;
+ max = tmp;
+ }
+ }
+ rk3288_dfi_start_hardware_counter(edev);
+
+ return busier_ch;
+}
+
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ int busier_ch;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
+ local_irq_restore(flags);
+
+ edata->load_count = info->ch_usage[busier_ch].access;
+ edata->total_count = info->ch_usage[busier_ch].total;
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3288_dfi_ops = {
+ .disable = rk3288_dfi_disable,
+ .enable = rk3288_dfi_enable,
+ .get_event = rk3288_dfi_get_event,
+ .set_event = rk3288_dfi_set_event,
+};
+
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
+}
+
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
+}
+
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
+{
+ rk3368_dfi_stop_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
+{
+ rk3368_dfi_start_hardware_counter(edev);
+
+ return 0;
+}
+
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
+{
+ return 0;
+}
+
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
+ struct devfreq_event_data *edata)
+{
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+ unsigned long flags;
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
+
+ local_irq_save(flags);
+
+ rk3368_dfi_stop_hardware_counter(edev);
+
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
+
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
+ edata->total_count = dfi_timer;
+
+ rk3368_dfi_start_hardware_counter(edev);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static const struct devfreq_event_ops rk3368_dfi_ops = {
+ .disable = rk3368_dfi_disable,
+ .enable = rk3368_dfi_enable,
+ .get_event = rk3368_dfi_get_event,
+ .set_event = rk3368_dfi_set_event,
};
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
{
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
void __iomem *dfi_regs = info->regs;
- u32 val;
- u32 ddr_type;
-
- /* get ddr type */
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
- RK3399_PMUGRF_DDRTYPE_MASK;
/* clear DDRMON_CTRL setting */
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
/* set ddr type to dfi */
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
+ else if (info->dram_type == LPDDR4)
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ else if (info->dram_type == DDR4)
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
/* enable count, use software mode */
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
rockchip_dfi_stop_hardware_counter(edev);
/* Find out which channel is busier */
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
+ if (!(info->ch_msk & BIT(i)))
+ continue;
+
info->ch_usage[i].total = readl_relaxed(dfi_regs +
DDRMON_CH0_COUNT_NUM + i * 20);
- tmp = info->ch_usage[i].access;
+
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
+ tmp = readl_relaxed(dfi_regs +
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ if (info->dram_type == LPDDR4)
+ tmp *= 8;
+ else
+ tmp *= 4;
+ info->ch_usage[i].access = tmp;
+
if (tmp > max) {
busier_ch = i;
max = tmp;
@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
rockchip_dfi_stop_hardware_counter(edev);
- clk_disable_unprepare(info->clk);
+ if (info->clk)
+ clk_disable_unprepare(info->clk);
return 0;
}
@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
int ret;
- ret = clk_prepare_enable(info->clk);
- if (ret) {
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
- return ret;
+ if (info->clk) {
+ ret = clk_prepare_enable(info->clk);
+ if (ret) {
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
+ ret);
+ return ret;
+ }
}
rockchip_dfi_start_hardware_counter(edev);
@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
{
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
int busier_ch;
+ unsigned long flags;
+ local_irq_save(flags);
busier_ch = rockchip_dfi_get_busier_ch(edev);
+ local_irq_restore(flags);
edata->load_count = info->ch_usage[busier_ch].access;
edata->total_count = info->ch_usage[busier_ch].total;
@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
.set_event = rockchip_dfi_set_event,
};
-static const struct of_device_id rockchip_dfi_id_match[] = {
- { .compatible = "rockchip,rk3399-dfi" },
- { },
-};
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+static __init int px30_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct resource *res;
+ u32 val;
-static int rockchip_dfi_probe(struct platform_device *pdev)
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
+ if (node) {
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_pmugrf))
+ return PTR_ERR(data->regmap_pmugrf);
+ }
+
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = 1;
+ data->clk = NULL;
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3128_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
{
- struct device *dev = &pdev->dev;
- struct rockchip_dfi *data;
- struct devfreq_event_desc *desc;
struct device_node *np = pdev->dev.of_node, *node;
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ desc->ops = &rk3128_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3288_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+ u32 val;
+
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
+ if (node) {
+ data->regmap_pmu = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_pmu))
+ return PTR_ERR(data->regmap_pmu);
+ }
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = READ_CH_INFO(val);
+
+ if (data->dram_type == DDR3)
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
+ RK3288_DDR3_SEL);
+ else
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
+ RK3288_LPDDR_SEL);
+
+ desc->ops = &rk3288_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3368_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device *dev = &pdev->dev;
+
+ if (!dev->parent || !dev->parent->of_node)
+ return -EINVAL;
+
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+
+ desc->ops = &rk3368_dfi_ops;
+
+ return 0;
+}
+
+static __init int rockchip_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node, *node;
+ u32 val;
data->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->regs))
@@ -201,21 +581,97 @@ static int rockchip_dfi_probe(struct pla
if (IS_ERR(data->regmap_pmu))
return PTR_ERR(data->regmap_pmu);
}
- data->dev = dev;
+
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = READ_CH_INFO(val);
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static __init int rk3328_dfi_init(struct platform_device *pdev,
+ struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc)
+{
+ struct device_node *np = pdev->dev.of_node, *node;
+ struct resource *res;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->regs))
+ return PTR_ERR(data->regs);
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ if (node) {
+ data->regmap_grf = syscon_node_to_regmap(node);
+ if (IS_ERR(data->regmap_grf))
+ return PTR_ERR(data->regmap_grf);
+ }
+
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
+ data->dram_type = READ_DRAMTYPE_INFO(val);
+ data->ch_msk = 1;
+ data->clk = NULL;
+
+ desc->ops = &rockchip_dfi_ops;
+
+ return 0;
+}
+
+static const struct of_device_id rockchip_dfi_id_match[] = {
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
+ { },
+};
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+
+static int rockchip_dfi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rockchip_dfi *data;
+ struct devfreq_event_desc *desc;
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
+ struct devfreq_event_desc *desc);
+
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
if (!desc)
return -ENOMEM;
- desc->ops = &rockchip_dfi_ops;
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
+ if (match) {
+ init = match->data;
+ if (init) {
+ if (init(pdev, data, desc))
+ return -EINVAL;
+ } else {
+ return 0;
+ }
+ } else {
+ return 0;
+ }
+
desc->driver_data = data;
desc->name = np->name;
data->desc = desc;
+ data->dev = dev;
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
if (IS_ERR(data->edev)) {
- dev_err(&pdev->dev,
- "failed to add devfreq-event device\n");
+ dev_err(dev, "failed to add devfreq-event device\n");
return PTR_ERR(data->edev);
}

29
patches-6.3/990-arm64-build-boot-image.patch
View File

@ -1,29 +0,0 @@
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 2d49aea0f..42c1a1410 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -159,8 +159,12 @@ endif
all: $(notdir $(KBUILD_IMAGE))
+DTBS := rk35*-nanopi*.dtb
Image vmlinuz.efi: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+ $(Q)scripts/mkkrnlimg $(objtree)/arch/arm64/boot/Image $(objtree)/kernel.img >/dev/null
+ @echo ' Image: kernel.img is ready'
+ $(Q)$(srctree)/scripts/mkimg --dtb $(DTBS)
Image.%: Image
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
diff --git a/scripts/Makefile b/scripts/Makefile
index e89179759..a5e21778b 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -9,6 +9,7 @@ hostprogs-always-$(CONFIG_BUILDTIME_TABLE_SORT) += sorttable
hostprogs-always-$(CONFIG_ASN1) += asn1_compiler
hostprogs-always-$(CONFIG_MODULE_SIG_FORMAT) += sign-file
hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE) += insert-sys-cert
+hostprogs-always-$(CONFIG_ARM64) += resource_tool mkkrnlimg
always-$(CONFIG_RUST) += target.json
filechk_rust_target = $< < include/config/auto.conf

12
patches-6.3/991-fix-arm64-kvm-for-openwrt.patch
View File

@ -1,12 +0,0 @@
--- a/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c
+++ b/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c
@@ -286,7 +286,9 @@ static void init_elf(const char *path)
assert_eq(elf.ehdr->e_ident[EI_CLASS], ELFCLASS64, "%u");
assert_eq(elf.ehdr->e_ident[EI_DATA], ELFENDIAN, "%u");
assert_eq(elf16toh(elf.ehdr->e_type), ET_REL, "%u");
+#ifdef EM_AARCH64
assert_eq(elf16toh(elf.ehdr->e_machine), EM_AARCH64, "%u");
+#endif
/* Populate fields of the global struct. */
elf.sh_table = section_by_off(elf64toh(elf.ehdr->e_shoff));

46
patches-6.3/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
View File

@ -1,46 +0,0 @@
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@immortalwrt.org>
Date: Mon, 18 Oct 2021 12:47:30 +0800
Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
and for better performance.
Co-development-by: gzelvis <gzelvis@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
---
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -33,6 +33,14 @@
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1125000 1125000 1250000>;
};
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1225000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1275000>;
+ };
};
cluster1_opp: opp-table-1 {
@@ -72,6 +80,14 @@
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1200000 1200000 1250000>;
};
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1325000>;
+ };
};
gpu_opp_table: opp-table-2 {

41
patches-6.3/999-linux-O3.patch
View File

@ -1,41 +0,0 @@
diff --git a/Makefile b/Makefile
index 56afd1509..10b3a59b4 100644
--- a/Makefile
+++ b/Makefile
@@ -823,6 +823,9 @@ KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)
ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE
KBUILD_CFLAGS += -O2
KBUILD_RUSTFLAGS += -Copt-level=2
+else ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3
+KBUILD_CFLAGS += -O3
+KBUILD_RUSTFLAGS += -Copt-level=3
else ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
KBUILD_RUSTFLAGS += -Copt-level=s
diff --git a/init/Kconfig b/init/Kconfig
index 94125d3b6..8ecbc5e96 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1405,7 +1405,7 @@ config INITRAMFS_PRESERVE_MTIME
choice
prompt "Compiler optimization level"
- default CC_OPTIMIZE_FOR_PERFORMANCE
+ default CC_OPTIMIZE_FOR_PERFORMANCE_O3
config CC_OPTIMIZE_FOR_PERFORMANCE
bool "Optimize for performance (-O2)"
@@ -1414,6 +1414,13 @@ config CC_OPTIMIZE_FOR_PERFORMANCE
with the "-O2" compiler flag for best performance and most
helpful compile-time warnings.
+config CC_OPTIMIZE_FOR_PERFORMANCE_O3
+ bool "Optimize more for performance (-O3)"
+ imply CC_DISABLE_WARN_MAYBE_UNINITIALIZED
+ help
+ Choosing this option will pass "-O3" to your compiler to optimize
+ the kernel yet more for performance.
+
config CC_OPTIMIZE_FOR_SIZE
bool "Optimize for size (-Os)"
help