From 55bef2d7e74998ff6d8ffe66cc2d044898b5339f Mon Sep 17 00:00:00 2001 From: sbwml Date: Thu, 29 Jun 2023 07:51:53 +0800 Subject: [PATCH] rockchip: patches-6.1: sync linux-6.1.36 --- ...ockchip-rk356x-Fix-PCIe-register-map.patch | 40 ------------------- 1 file changed, 40 deletions(-) delete mode 100644 patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch diff --git a/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch b/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch deleted file mode 100644 index 1752b98..0000000 --- a/patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001 -From: Andrew Powers-Holmes -Date: Sat, 12 Nov 2022 22:41:26 +1100 -Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and - range mappings - -The register and range mappings for the PCIe controller in Rockchip's -RK356x SoCs are incorrect. Replace them with corrected values from the -vendor BSP sources, updated to match current DT schema. - -Tested-by: Ondrej Jirman -Signed-off-by: Andrew Powers-Holmes ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------ - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++--- - 2 files changed, 12 insertions(+), 9 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 { - compatible = "rockchip,rk3568-pcie"; - reg = <0x3 0xc0000000 0x0 0x00400000>, - <0x0 0xfe260000 0x0 0x00010000>, -- <0x3 0x3f000000 0x0 0x01000000>; -+ <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - interrupts = , - , -@@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 { - phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; -- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 -- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; -+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, -+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; - resets = <&cru SRST_PCIE20_POWERUP>; - reset-names = "pipe"; - #address-cells = <3>;