rockchip: init linux-6.12

Signed-off-by: sbwml <admin@cooluc.com>

Makefile

@@ -8,7 +8,7 @@ FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-pa
 SUBTARGETS:=armv8
 
 KERNEL_PATCHVER:=6.6
-KERNEL_TESTING_PATCHVER:=6.11
+KERNEL_TESTING_PATCHVER:=6.12
 
 define Target/Description
 	Build firmware image for Rockchip SoC devices.

armv8/config-6.12

@@ -21,7 +21,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARCH_WANTS_NO_INSTR=y
 CONFIG_ARCH_WANTS_THP_SWAP=y
 CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_BRBE=y
 CONFIG_ARM64_CNP=y
 CONFIG_ARM64_EPAN=y
 CONFIG_ARM64_ERRATUM_2051678=y
@@ -120,6 +119,7 @@ CONFIG_CLK_RK3328=y
 CONFIG_CLK_RK3368=y
 CONFIG_CLK_RK3399=y
 CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3576=y
 CONFIG_CLK_RK3588=y
 CONFIG_CLKSRC_MMIO=y
 CONFIG_CLONE_BACKWARDS=y
@@ -309,7 +309,7 @@ CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_HWMON=y
-CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
 CONFIG_HW_RANDOM=y
 CONFIG_HWSPINLOCK=y
 CONFIG_I2C_BOARDINFO=y

files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi

@@ -518,6 +518,9 @@
 };
 
 &rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;
+
 	status = "okay";
 };
 

patches-6.11/002-add-hwrng-for-rk3568.patch

@@ -1,383 +0,0 @@
-From 31cde3e68c30242394fc2c6598a9a0540b340588 Mon Sep 17 00:00:00 2001
-From: sbwml <admin@cooluc.com>
-Date: Mon, 23 Sep 2024 04:45:24 +0800
-Subject: [PATCH] add hwrng for rk3568
-
-Signed-off-by: sbwml <admin@cooluc.com>
----
- .../bindings/rng/rockchip,rk3568-rng.yaml     |  60 +++++
- arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  10 +
- drivers/char/hw_random/Kconfig                |  14 +
- drivers/char/hw_random/Makefile               |   1 +
- drivers/char/hw_random/rk3568-rng.c           | 249 ++++++++++++++++++
- 5 files changed, 334 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
- create mode 100644 drivers/char/hw_random/rk3568-rng.c
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
-@@ -0,0 +1,60 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Rockchip TRNG
-+
-+description: True Random Number Generator for some Rockchip SoCs
-+
-+maintainers:
-+  - Aurelien Jarno <aurelien@aurel32.net>
-+
-+properties:
-+  compatible:
-+    enum:
-+      - rockchip,rk3568-rng
-+
-+  reg:
-+    maxItems: 1
-+
-+  clocks:
-+    items:
-+      - description: TRNG clock
-+      - description: TRNG AHB clock
-+
-+  clock-names:
-+    items:
-+      - const: trng_clk
-+      - const: trng_hclk
-+
-+  resets:
-+    maxItems: 1
-+
-+required:
-+  - compatible
-+  - reg
-+  - clocks
-+  - clock-names
-+  - resets
-+
-+additionalProperties: false
-+
-+examples:
-+  - |
-+    #include <dt-bindings/clock/rk3568-cru.h>
-+    bus {
-+      #address-cells = <2>;
-+      #size-cells = <2>;
-+
-+      rng@fe388000 {
-+        compatible = "rockchip,rk3568-rng";
-+        reg = <0x0 0xfe388000 0x0 0x4000>;
-+        clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
-+        clock-names = "trng_clk", "trng_hclk";
-+        resets = <&cru SRST_TRNG_NS>;
-+      };
-+    };
-+
-+...
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1855,6 +1855,16 @@
- 		};
- 	};
- 
-+	rng: rng@fe388000 {
-+		compatible = "rockchip,rk3568-rng";
-+		reg = <0x0 0xfe388000 0x0 0x4000>;
-+		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
-+		clock-names = "trng_clk", "trng_hclk";
-+		resets = <&cru SRST_TRNG_NS>;
-+		reset-names = "reset";
-+		status = "disabled";
-+	};
-+
- 	pinctrl: pinctrl {
- 		compatible = "rockchip,rk3568-pinctrl";
- 		rockchip,grf = <&grf>;
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -383,6 +383,20 @@ config HW_RANDOM_STM32
- 
- 	  If unsure, say N.
- 
-+config HW_RANDOM_ROCKCHIP_RK3568
-+	tristate "Rockchip RK3568 True Random Number Generator"
-+	depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
-+	depends on HAS_IOMEM
-+	default HW_RANDOM
-+	help
-+	  This driver provides kernel-side support for the True Random Number
-+	  Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called rockchip-rng.
-+
-+	  If unsure, say Y.
-+
- config HW_RANDOM_PIC32
- 	tristate "Microchip PIC32 Random Number Generator support"
- 	depends on MACH_PIC32 || COMPILE_TEST
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
- obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
- obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP_RK3568) += rk3568-rng.o
- obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
- obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
- obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
---- /dev/null
-+++ b/drivers/char/hw_random/rk3568-rng.c
-@@ -0,0 +1,249 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
-+ *
-+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
-+ * Copyright (c) 2022, Aurelien Jarno
-+ * Authors:
-+ *  Lin Jinhan <troy.lin@rock-chips.com>
-+ *  Aurelien Jarno <aurelien@aurel32.net>
-+ */
-+#include <linux/clk.h>
-+#include <linux/hw_random.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm_runtime.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#define RK_RNG_AUTOSUSPEND_DELAY	100
-+#define RK_RNG_MAX_BYTE			32
-+#define RK_RNG_POLL_PERIOD_US		100
-+#define RK_RNG_POLL_TIMEOUT_US		10000
-+
-+/*
-+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
-+ * a tradeoff between speed and quality and has been adjusted to get a quality
-+ * of ~900 (~90% of FIPS 140-2 successes).
-+ */
-+#define RK_RNG_SAMPLE_CNT		1000
-+
-+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
-+#define TRNG_RST_CTL			0x0004
-+#define TRNG_RNG_CTL			0x0400
-+#define TRNG_RNG_CTL_LEN_64_BIT		(0x00 << 4)
-+#define TRNG_RNG_CTL_LEN_128_BIT	(0x01 << 4)
-+#define TRNG_RNG_CTL_LEN_192_BIT	(0x02 << 4)
-+#define TRNG_RNG_CTL_LEN_256_BIT	(0x03 << 4)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_0	(0x00 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_1	(0x01 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_2	(0x02 << 2)
-+#define TRNG_RNG_CTL_OSC_RING_SPEED_3	(0x03 << 2)
-+#define TRNG_RNG_CTL_ENABLE		BIT(1)
-+#define TRNG_RNG_CTL_START		BIT(0)
-+#define TRNG_RNG_SAMPLE_CNT		0x0404
-+#define TRNG_RNG_DOUT_0			0x0410
-+#define TRNG_RNG_DOUT_1			0x0414
-+#define TRNG_RNG_DOUT_2			0x0418
-+#define TRNG_RNG_DOUT_3			0x041c
-+#define TRNG_RNG_DOUT_4			0x0420
-+#define TRNG_RNG_DOUT_5			0x0424
-+#define TRNG_RNG_DOUT_6			0x0428
-+#define TRNG_RNG_DOUT_7			0x042c
-+
-+struct rk_rng {
-+	struct hwrng rng;
-+	void __iomem *base;
-+	struct reset_control *rst;
-+	int clk_num;
-+	struct clk_bulk_data *clk_bulks;
-+};
-+
-+/* The mask determine the bits that are updated */
-+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
-+{
-+	writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
-+}
-+
-+static int rk_rng_init(struct hwrng *rng)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+	u32 reg;
-+	int ret;
-+
-+	/* start clocks */
-+	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
-+	if (ret < 0) {
-+		dev_err((struct device *) rk_rng->rng.priv,
-+			"Failed to enable clks %d\n", ret);
-+		return ret;
-+	}
-+
-+	/* set the sample period */
-+	writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
-+
-+	/* set osc ring speed and enable it */
-+	reg = TRNG_RNG_CTL_LEN_256_BIT |
-+		   TRNG_RNG_CTL_OSC_RING_SPEED_0 |
-+		   TRNG_RNG_CTL_ENABLE;
-+	rk_rng_write_ctl(rk_rng, reg, 0xffff);
-+
-+	return 0;
-+}
-+
-+static void rk_rng_cleanup(struct hwrng *rng)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+	u32 reg;
-+
-+	/* stop TRNG */
-+	reg = 0;
-+	rk_rng_write_ctl(rk_rng, reg, 0xffff);
-+
-+	/* stop clocks */
-+	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
-+}
-+
-+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
-+{
-+	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
-+	u32 reg;
-+	int ret = 0;
-+	int i;
-+
-+	pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
-+
-+	/* Start collecting random data */
-+	reg = TRNG_RNG_CTL_START;
-+	rk_rng_write_ctl(rk_rng, reg, reg);
-+
-+	ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
-+				 !(reg & TRNG_RNG_CTL_START),
-+				 RK_RNG_POLL_PERIOD_US,
-+				 RK_RNG_POLL_TIMEOUT_US);
-+	if (ret < 0)
-+		goto out;
-+
-+	/* Read random data stored in the registers */
-+	ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
-+	for (i = 0; i < ret; i += 4) {
-+		*(u32 *)(buf + i) = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
-+	}
-+
-+out:
-+	pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
-+	pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
-+
-+	return ret;
-+}
-+
-+static int rk_rng_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct rk_rng *rk_rng;
-+	int ret;
-+
-+	rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
-+	if (!rk_rng)
-+		return -ENOMEM;
-+
-+	rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
-+	if (IS_ERR(rk_rng->base))
-+		return PTR_ERR(rk_rng->base);
-+
-+	rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
-+	if (rk_rng->clk_num < 0)
-+		return dev_err_probe(dev, rk_rng->clk_num,
-+				     "Failed to get clks property\n");
-+
-+	rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
-+	if (IS_ERR(rk_rng->rst))
-+		return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
-+				     "Failed to get reset property\n");
-+
-+	reset_control_assert(rk_rng->rst);
-+	udelay(2);
-+	reset_control_deassert(rk_rng->rst);
-+
-+	platform_set_drvdata(pdev, rk_rng);
-+
-+	rk_rng->rng.name = dev_driver_string(dev);
-+#ifndef CONFIG_PM
-+	rk_rng->rng.init = rk_rng_init;
-+	rk_rng->rng.cleanup = rk_rng_cleanup;
-+#endif
-+	rk_rng->rng.read = rk_rng_read;
-+	rk_rng->rng.priv = (unsigned long) dev;
-+	rk_rng->rng.quality = 900;
-+
-+	pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
-+	pm_runtime_use_autosuspend(dev);
-+	pm_runtime_enable(dev);
-+
-+	ret = devm_hwrng_register(dev, &rk_rng->rng);
-+	if (ret)
-+		return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
-+
-+	dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
-+
-+	return 0;
-+}
-+
-+static void rk_rng_remove(struct platform_device *pdev)
-+{
-+	pm_runtime_disable(&pdev->dev);
-+}
-+
-+#ifdef CONFIG_PM
-+static int rk_rng_runtime_suspend(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	rk_rng_cleanup(&rk_rng->rng);
-+
-+	return 0;
-+}
-+
-+static int rk_rng_runtime_resume(struct device *dev)
-+{
-+	struct rk_rng *rk_rng = dev_get_drvdata(dev);
-+
-+	return rk_rng_init(&rk_rng->rng);
-+}
-+#endif
-+
-+static const struct dev_pm_ops rk_rng_pm_ops = {
-+	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
-+				rk_rng_runtime_resume, NULL)
-+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-+				pm_runtime_force_resume)
-+};
-+
-+static const struct of_device_id rk_rng_dt_match[] = {
-+	{
-+		.compatible = "rockchip,rk3568-rng",
-+	},
-+	{},
-+};
-+
-+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
-+
-+static struct platform_driver rk_rng_driver = {
-+	.driver	= {
-+		.name	= "rk3568-rng",
-+		.pm	= &rk_rng_pm_ops,
-+		.of_match_table = rk_rng_dt_match,
-+	},
-+	.probe	= rk_rng_probe,
-+	.remove_new = rk_rng_remove,
-+};
-+
-+module_platform_driver(rk_rng_driver);
-+
-+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
-+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
-+MODULE_LICENSE("GPL v2");

patches-6.11/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch

@@ -1,46 +0,0 @@
-From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@immortalwrt.org>
-Date: Mon, 18 Oct 2021 12:47:30 +0800
-Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
-
-It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
-and for better performance.
-
-Co-development-by: gzelvis <gzelvis@gmail.com>
-Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
----
- arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
-@@ -33,6 +33,14 @@
- 			opp-hz = /bits/ 64 <1416000000>;
- 			opp-microvolt = <1125000 1125000 1250000>;
- 		};
-+		opp06 {
-+			opp-hz = /bits/ 64 <1608000000>;
-+			opp-microvolt = <1225000>;
-+		};
-+		opp07 {
-+			opp-hz = /bits/ 64 <1800000000>;
-+			opp-microvolt = <1275000>;
-+		};
- 	};
- 
- 	cluster1_opp: opp-table-1 {
-@@ -72,6 +80,14 @@
- 			opp-hz = /bits/ 64 <1800000000>;
- 			opp-microvolt = <1200000 1200000 1250000>;
- 		};
-+		opp08 {
-+			opp-hz = /bits/ 64 <2016000000>;
-+			opp-microvolt = <1250000>;
-+		};
-+		opp09 {
-+			opp-hz = /bits/ 64 <2208000000>;
-+			opp-microvolt = <1325000>;
-+		};
- 	};
- 
- 	gpu_opp_table: opp-table-2 {

patches-6.12/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch

@@ -61,9 +61,9 @@
  
 --- a/drivers/usb/host/xhci-plat.c
 +++ b/drivers/usb/host/xhci-plat.c
-@@ -259,6 +259,9 @@ int xhci_plat_probe(struct platform_devi
+@@ -265,6 +265,9 @@ int xhci_plat_probe(struct platform_devi
- 		if (device_property_read_bool(tmpdev, "write-64-hi-lo-quirk"))
+ 		if (device_property_read_bool(tmpdev, "xhci-skip-phy-init-quirk"))
- 			xhci->quirks |= XHCI_WRITE_64_HI_LO;
+ 			xhci->quirks |= XHCI_SKIP_PHY_INIT;
  
 +		if (device_property_read_bool(tmpdev, "xhci-trb-ent-quirk"))
 +			xhci->quirks |= XHCI_TRB_ENT_QUIRK;
@@ -73,7 +73,7 @@
  	}
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3555,6 +3555,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3563,6 +3563,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	bool more_trbs_coming = true;
  	bool need_zero_pkt = false;
  	bool first_trb = true;
@@ -81,7 +81,7 @@
  	unsigned int num_trbs;
  	unsigned int start_cycle, num_sgs = 0;
  	unsigned int enqd_len, block_len, trb_buff_len, full_len;
-@@ -3591,6 +3592,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3599,6 +3600,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
  		need_zero_pkt = true;
  
@@ -95,7 +95,7 @@
  	td = &urb_priv->td[0];
  
  	/*
-@@ -3619,6 +3627,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3627,6 +3635,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  			first_trb = false;
  			if (start_cycle == 0)
  				field |= TRB_CYCLE;
@@ -109,7 +109,7 @@
  		} else
  			field |= ring->cycle_state;
  
-@@ -3627,6 +3642,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3635,6 +3650,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  		 */
  		if (enqd_len + trb_buff_len < full_len) {
  			field |= TRB_CHAIN;
@@ -132,7 +132,7 @@
  #define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
  /* How much data is left before the 64KB boundary? */
  #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
-@@ -1569,6 +1573,7 @@ struct xhci_hcd {
+@@ -1564,6 +1568,7 @@ struct xhci_hcd {
  #define XHCI_STATE_HALTED	(1 << 1)
  #define XHCI_STATE_REMOVING	(1 << 2)
  	unsigned long long	quirks;

patches-6.12/013-rk3399-add-dwc3-xhci-usb-trb-quirk.patch

@@ -1,5 +1,5 @@
---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
 @@ -556,6 +556,7 @@
  			snps,dis_enblslpm_quirk;
  			snps,dis-u2-freeclk-exists-quirk;

patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/Kconfig
 +++ b/arch/arm64/Kconfig
-@@ -1285,6 +1285,14 @@ config SOCIONEXT_SYNQUACER_PREITS
+@@ -1302,6 +1302,14 @@ config SOCIONEXT_SYNQUACER_PREITS
  
  	  If unsure, say Y.
  

patches-6.12/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch

@@ -0,0 +1,32 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -35,6 +35,14 @@
+ 			opp-hz = /bits/ 64 <1416000000>;
+ 			opp-microvolt = <1125000 1125000 1250000>;
+ 		};
++		opp06 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1225000>;
++		};
++		opp07 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1275000>;
++		};
+ 	};
+ 
+ 	cluster1_opp: opp-table-1 {
+@@ -74,6 +82,14 @@
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1200000 1200000 1250000>;
+ 		};
++		opp08 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <1250000>;
++		};
++		opp09 {
++			opp-hz = /bits/ 64 <2208000000>;
++			opp-microvolt = <1325000>;
++		};
+ 	};
+ 
+ 	gpu_opp_table: opp-table-2 {

patches-6.12/993-rockchip-rk356x-adjust-CPU-voltage.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -233,7 +233,7 @@
+@@ -272,7 +272,7 @@
  &cpu0_opp_table {
  	opp-1992000000 {
  		opp-hz = /bits/ 64 <1992000000>;