init

Makefile

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+include $(TOPDIR)/rules.mk
+
+BOARD:=rockchip
+BOARDNAME:=Rockchip
+FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
+SUBTARGETS:=armv8
+
+KERNEL_PATCHVER:=6.1
+
+define Target/Description
+	Build firmware image for Rockchip SoC devices.
+endef
+
+include $(INCLUDE_DIR)/target.mk
+
+DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \
+					automount autocore-arm fdisk e2fsprogs ethtool
+
+KERNELNAME:=Image dtbs
+
+$(eval $(call BuildTarget))

armv8/base-files/etc/board.d/01_leds

@@ -0,0 +1,21 @@
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board=$(board_name)
+boardname="${board##*,}"
+
+board_config_update
+
+case $board in
+friendlyarm,nanopi-r5s)
+	ucidef_set_led_default "power" "POWER" "red:power" "1"
+	ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
+	ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
+	ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2"
+	;;
+esac
+
+board_config_flush
+
+exit 0

armv8/base-files/etc/board.d/02_network

@@ -0,0 +1,51 @@
+
+. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
+
+rockchip_setup_interfaces()
+{
+	local board="$1"
+
+	case "$board" in
+	friendlyarm,nanopi-r5s)
+		ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0'
+		;;
+	*)
+		ucidef_set_interface_lan 'eth0'
+		;;
+	esac
+}
+
+nanopi_r5s_generate_mac()
+{
+	local emmc_hash=$(sha256sum /sys/block/mmcblk*/device/cid | head -n 1)
+	local mac_base=$(macaddr_canonicalize "$(echo "${emmc_hash}" | dd bs=1 count=12 2>/dev/null)")
+	echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")"
+}
+
+rockchip_setup_macs()
+{
+	local board="$1"
+	local lan_mac=""
+	local wan_mac=""
+	local label_mac=""
+
+	case "$board" in
+	friendlyarm,nanopi-r5s)
+		wan_mac=$(nanopi_r5s_generate_mac)
+		lan_mac=$(macaddr_add "$wan_mac" +1)
+		;;
+	esac
+
+	[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
+	[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
+	[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
+}
+
+board_config_update
+board=$(board_name)
+rockchip_setup_interfaces $board
+rockchip_setup_macs $board
+board_config_flush
+
+exit 0

armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity

@@ -0,0 +1,44 @@
+#!/bin/sh
+
+[ "$ACTION" = add ] || exit
+
+get_device_irq() {
+	local device="$1"
+	local line
+	local seconds="0"
+
+	# wait up to 10 seconds for the irq/device to appear
+	while [ "${seconds}" -le 10 ]; do
+		line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
+		seconds="$(( seconds + 2 ))"
+		sleep 2
+	done
+	echo ${line} | sed 's/:.*//'
+}
+
+set_interface_core() {
+	local core_mask="$1"
+	local interface="$2"
+	local device="$3"
+
+	[ -z "${device}" ] && device="$interface"
+
+	local irq=$(get_device_irq "$device")
+
+	echo "${core_mask}" > /proc/irq/${irq}/smp_affinity
+}
+
+case "$(board_name)" in
+friendlyarm,nanopi-r5s)
+	set_interface_core 8 "eth0"
+	echo f > /sys/class/net/eth0/queues/rx-0/rps_cpus
+	set_interface_core 4 "eth1-0"
+	set_interface_core 4 "eth1-16"
+	set_interface_core 4 "eth1-18"
+	echo b > /sys/class/net/eth1/queues/rx-0/rps_cpus
+	set_interface_core 2 "eth2-0"
+	set_interface_core 2 "eth2-16"
+	set_interface_core 2 "eth2-18"
+	echo d > /sys/class/net/eth2/queues/rx-0/rps_cpus
+	;;
+esac

armv8/base-files/etc/init.d/drm-panfrost

@@ -0,0 +1,3 @@
+#!/bin/sh /etc/rc.common
+
+chmod -R 777 /dev/dri

armv8/base-files/etc/init.d/fa-fancontrol

@@ -0,0 +1,7 @@
+#!/bin/sh /etc/rc.common
+
+START=21
+start() {
+    /usr/bin/fa-fancontrol.sh &
+}
+

armv8/base-files/etc/init.d/sysled

@@ -0,0 +1,7 @@
+#!/bin/sh /etc/rc.common
+
+START=99
+start() {
+    sleep 3m && /etc/init.d/led restart > /dev/null 2>&1 &
+}
+

armv8/base-files/etc/rc.d/S15drm-panfrost

@@ -0,0 +1 @@
+../init.d/drm-panfrost

armv8/base-files/etc/rc.d/S21fa-fancontrol

@@ -0,0 +1 @@
+../init.d/fa-fancontrol

armv8/base-files/etc/rc.d/S99sysled

@@ -0,0 +1 @@
+../init.d/sysled

armv8/base-files/lib/preinit/79_move_config

@@ -0,0 +1,16 @@
+move_config() {
+	local partdev
+
+	. /lib/upgrade/common.sh
+
+	if export_bootdevice && export_partdevice partdev 1; then
+		if mount -o rw,noatime "/dev/$partdev" /mnt; then
+			if [ -f "/mnt/$BACKUP_FILE" ]; then
+				mv -f "/mnt/$BACKUP_FILE" /
+			fi
+			umount /mnt
+		fi
+	fi
+}
+
+boot_hook_add preinit_mount_root move_config

armv8/base-files/lib/upgrade/platform.sh

@@ -0,0 +1,86 @@
+platform_check_image() {
+	local diskdev partdev diff
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		echo "Unable to determine upgrade device"
+		return 1
+	}
+
+	get_partitions "/dev/$diskdev" bootdisk
+
+	#extract the boot sector from the image
+	get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null
+
+	get_partitions /tmp/image.bs image
+
+	#compare tables
+	diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+
+	rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
+
+	if [ -n "$diff" ]; then
+		echo "Partition layout has changed. Full image will be written."
+		ask_bool 0 "Abort" && exit 1
+		return 0
+	fi
+}
+
+platform_copy_config() {
+	local partdev
+
+	if export_partdevice partdev 1; then
+		mount -o rw,noatime "/dev/$partdev" /mnt
+		cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
+		umount /mnt
+	fi
+}
+
+platform_do_upgrade() {
+	local diskdev partdev diff
+
+	export_bootdevice && export_partdevice diskdev 0 || {
+		echo "Unable to determine upgrade device"
+		return 1
+	}
+
+	sync
+
+	if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
+		get_partitions "/dev/$diskdev" bootdisk
+
+		#extract the boot sector from the image
+		get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b
+
+		get_partitions /tmp/image.bs image
+
+		#compare tables
+		diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
+	else
+		diff=1
+	fi
+
+	if [ -n "$diff" ]; then
+		get_image "$@" | dd of="/dev/$diskdev" bs=4096 conv=fsync
+
+		# Separate removal and addtion is necessary; otherwise, partition 1
+		# will be missing if it overlaps with the old partition 2
+		partx -d - "/dev/$diskdev"
+		partx -a - "/dev/$diskdev"
+
+		return 0
+	fi
+
+	#iterate over each partition from the image and write it to the boot disk
+	while read part start size; do
+		if export_partdevice partdev $part; then
+			echo "Writing image to /dev/$partdev..."
+			get_image "$@" | dd of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
+		else
+			echo "Unable to find partition $part device, skipped."
+		fi
+	done < /tmp/partmap.image
+
+	#copy partition uuid
+	echo "Writing new UUID to /dev/$diskdev..."
+	get_image "$@" | dd of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
+}

armv8/base-files/usr/bin/cputemp.sh

@@ -0,0 +1,14 @@
+#!/bin/bash
+
+while true
+do
+echo "-----------------"
+echo "Curr freq: `cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq`,`cat /sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq`"
+echo "Temp: `cat /sys/class/thermal/thermal_zone0/temp`"
+if [ -d /sys/devices/platform/pwm-fan ]; then
+    CUR=`cat /sys/devices/virtual/thermal/cooling_device0/cur_state`
+    MAX=`cat /sys/devices/virtual/thermal/cooling_device0/max_state`
+    echo "Fan Level: ${CUR}/${MAX}"
+fi
+sleep 5
+done

armv8/base-files/usr/bin/fa-fancontrol-direct.sh

@@ -0,0 +1,69 @@
+#!/bin/bash
+
+# determine fan controller
+if [ -d /sys/devices/platform/pwm-fan ]; then
+    echo "pls use /usr/bin/fa-fancontrol.sh."
+    exit 1
+fi
+
+if [ ! -d /sys/class/pwm/pwmchip1 ]; then
+    echo "this model does not support pwm."
+    exit 1
+fi
+if [ ! -d /sys/class/pwm/pwmchip1/pwm0 ]; then
+    echo 0 > /sys/class/pwm/pwmchip1/export
+fi
+sleep 1
+while [ ! -d /sys/class/pwm/pwmchip1/pwm0 ];
+do
+    sleep 1
+done
+ISENABLE=`cat /sys/class/pwm/pwmchip1/pwm0/enable`
+if [ $ISENABLE -eq 1 ]; then
+    echo 0 > /sys/class/pwm/pwmchip1/pwm0/enable
+fi
+echo 50000 > /sys/class/pwm/pwmchip1/pwm0/period
+echo 1 > /sys/class/pwm/pwmchip1/pwm0/enable
+
+# max speed run 5s
+echo 46990 > /sys/class/pwm/pwmchip1/pwm0/duty_cycle
+sleep 5
+echo 25000 > /sys/class/pwm/pwmchip1/pwm0/duty_cycle
+
+# declare -a CpuTemps=(55000 43000 38000 32000)
+# declare -a PwmDutyCycles=(1000 20000 30000 45000)
+
+declare -a CpuTemps=(75000 63000 58000 52000)
+declare -a PwmDutyCycles=(25000 35000 45000 46990)
+
+declare -a Percents=(100 75 50 25)
+DefaultDuty=49990
+DefaultPercents=0
+
+while true
+do
+	temp=$(cat /sys/class/thermal/thermal_zone0/temp)
+	INDEX=0
+	FOUNDTEMP=0
+	DUTY=$DefaultDuty
+	PERCENT=$DefaultPercents
+	
+	for i in 0 1 2 3; do
+		if [ $temp -gt ${CpuTemps[$i]} ]; then
+			INDEX=$i
+			FOUNDTEMP=1
+			break
+		fi	
+	done
+	if [ ${FOUNDTEMP} == 1 ]; then
+		DUTY=${PwmDutyCycles[$i]}
+		PERCENT=${Percents[$i]}
+	fi
+
+	echo $DUTY > /sys/class/pwm/pwmchip1/pwm0/duty_cycle;
+
+        # echo "temp: $temp, duty: $DUTY, ${PERCENT}%"
+        # cat /sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_cur_freq
+
+	sleep 2s;
+done

armv8/base-files/usr/bin/fa-fancontrol.sh

@@ -0,0 +1,36 @@
+#!/bin/bash
+
+# determine fan controller
+if [ -d /sys/devices/platform/pwm-fan ]; then
+    (cd /sys/devices/virtual/thermal/thermal_zone0 && {        
+        logger -p user.info -t "pwmfan" "set the conditions for fan"
+        [ -f trip_point_3_temp ] && {
+            # select fan level 1
+            echo 50000 > trip_point_3_temp
+        }
+        [ -f trip_point_4_temp ] && {
+            # select fan level 2-4
+            echo 55000 > trip_point_4_temp
+        }
+    })
+
+    (cd /sys/devices/virtual/thermal/cooling_device0 && {
+        TYPE=`cat type`
+        if [ $TYPE = 'pwm-fan' ]; then
+            # run 5s
+            for i in `seq 1 5`; do
+                logger -p user.info -t "pwmfan" "start to spin ${i}/5"
+                echo 3 > cur_state
+                sleep 1
+            done
+            logger -p user.info -t "pwmfan" "set to auto"
+            echo 0 > cur_state
+        fi
+    })
+else
+    logger -p user.info -t "pwmfan" "not found cooling device"
+    if [ -d /sys/class/pwm/pwmchip1 ]; then
+        nohup /usr/bin/fa-fancontrol-direct.sh&
+    fi
+fi
+

armv8/config-6.1

@@ -0,0 +1,787 @@
+CONFIG_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_ERRATUM_1742098=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_MODULE_PLTS=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+# CONFIG_ARM64_SW_TTBR0_PAN is not set
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_FFA_SMCCC=y
+CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_MHU_V2=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMCCC_SOC_ID=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ATA=y
+CONFIG_ATA_GENERIC=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINARY_PRINTF=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLOCK_LEGACY_AUTOLOAD=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_CACHEFILES_ERROR_INJECTION is not set
+# CONFIG_CACHEFILES_ONDEMAND is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CHARGER_GPIO=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+# CONFIG_COMMON_CLK_RS9_PCIE is not set
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEV_ROCKCHIP=y
+CONFIG_CRYPTO_DEV_ROCKCHIP2=y
+# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM3_GENERIC=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+# CONFIG_HARDENED_USERCOPY is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+# CONFIG_HAS_IOPORT_MAP is not set
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+# CONFIG_HISI_PTT is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INET_TABLE_PERTURB_ORDER=16
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_RK805_PWRKEY=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IO_URING=y
+# CONFIG_IR_GPIO_TX is not set
+# CONFIG_IR_IMON_DECODER is not set
+# CONFIG_IR_IMON_RAW is not set
+# CONFIG_IR_MCE_KBD_DECODER is not set
+# CONFIG_IR_PWM_TX is not set
+# CONFIG_IR_RCMM_DECODER is not set
+# CONFIG_IR_SANYO_DECODER is not set
+# CONFIG_IR_SERIAL is not set
+# CONFIG_IR_SHARP_DECODER is not set
+# CONFIG_IR_SPI is not set
+# CONFIG_IR_TOY is not set
+# CONFIG_IR_XMP_DECODER is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+CONFIG_KVM=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_PCI=y
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_HSQ=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_USDHI6ROL0=y
+CONFIG_MMC_USHC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+# CONFIG_NET_DSA_REALTEK is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NFSD_V4_2_INTER_SSC is not set
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NVMEM_ROCKCHIP_EFUSE is not set
+# CONFIG_NVMEM_ROCKCHIP_OTP is not set
+# CONFIG_NVHE_EL2_DEBUG is not set
+# CONFIG_OCTEON_EP is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_XPCS=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SYSFS=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_ARM_SCMI is not set
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_ERRATUM_114514=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+# CONFIG_ROCKCHIP_LVDS is not set
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_RGB is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SDIO_UART=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FINTEK=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_PCIPS2=y
+CONFIG_SERIO_RAW=y
+CONFIG_SG_POOL=y
+# CONFIG_SHADOW_CALL_STACK is not set
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+# CONFIG_SND_SOC_ROCKCHIP is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+# CONFIG_TYPEC_DP_ALTMODE is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UACCE is not set
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USERIO=y
+CONFIG_VENDOR_FRIENDLYELEC=y
+CONFIG_VIDEOMODE_HELPERS=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y

armv8/target.mk

@@ -0,0 +1,8 @@
+ARCH:=aarch64
+SUBTARGET:=armv8
+BOARDNAME:=RK33xx,RK35xx boards (64 bit)
+
+define Target/Description
+	Build firmware image for Rockchip RK33xx,RK35xx devices.
+	This firmware features a 64 bit kernel.
+endef

files-6.1/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "FriendlyElec NanoPi R5S";
+	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
+
+	aliases {
+		ethernet0 = &gmac0;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+
+		led-boot = &sys_led;
+		led-failsafe = &sys_led;
+		led-running = &sys_led;
+		led-upgrade = &sys_led;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 18 102 170 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vcc5v0_sysp>;
+		pwms = <&pwm0 0 50000 0>;
+	};
+
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
+	cspmu: cspmu@fd90c000 {
+		compatible = "rockchip,cspmu";
+		reg = <0x0 0xfd90c000 0x0 0x1000>,
+			<0x0 0xfd90d000 0x0 0x1000>,
+			<0x0 0xfd90e000 0x0 0x1000>,
+			<0x0 0xfd90f000 0x0 0x1000>;
+	};
+
+	gpio-key {
+		compatible = "gpio-key";
+		pinctrl-names = "default";
+		pinctrl-0 = <&key1_pin>;
+
+		button@1 {
+			debounce-interval = <50>;
+			gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: led-sys {
+			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+			label = "red:power";
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+
+		wan_led: led-wan {
+			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+			label = "green:wan";
+			pinctrl-names = "default";
+			pinctrl-0 = <&wan_led_pin>;
+		};
+
+		lan1_led: led-lan1 {
+			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
+			label = "green:lan1";
+			pinctrl-names = "default";
+			pinctrl-0 = <&lan1_led_pin>;
+		};
+
+		lan2_led: led-lan2 {
+			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
+			label = "green:lan2";
+			pinctrl-names = "default";
+			pinctrl-0 = <&lan2_led_pin>;
+		};
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	vdd_usbc: vdd-usbc {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usbc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <200000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc3v3_pcie>;
+	};
+
+	vcc3v3_ngff: vcc3v3-ngff-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_ngff";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc3v3_pcie>;
+	};
+
+	vcc5v0_usb: vcc5v0_usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc5v0_usb_host: vcc5v0-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_sysp: vcc5v0-sysp {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sysp";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	vcc5v0_usb_otg: vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+};
+
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	tx_delay = <0x3c>;
+	rx_delay = <0x2f>;
+
+	phy-handle = <&rgmii_phy0>;
+	status = "okay";
+};
+
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-init-microvolt = <900000>;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+
+&i2c5 {
+	status = "okay";
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gmac_int>;
+	};
+};
+
+&pcie30phy {
+	data-lanes = <1 2>;
+	status = "okay";
+};
+
+&pcie3x1 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_ngff>;
+	status = "okay";
+};
+
+&pcie3x2 {
+	num-lanes = <1>;
+	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pcie2x1 {
+	num-viewport = <4>;
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-leds {
+
+		sys_led_pin: sys-led-pin {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan1_led_pin: lan1-led-pin {
+			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lan2_led_pin: lan2-led-pin {
+			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		gmac_int: gmac-int {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-key {
+		key1_pin: key1-pin {
+			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rtc {
+		rtc_int: rtc-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm4 {
+	status = "disabled";
+};
+
+&pwm5 {
+	status = "disabled";
+};
+
+&pwm7 {
+	status = "disabled";
+};
+
+&rng {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sata2 {
+	status = "disabled";
+};
+
+&sdhci {
+	bus-width = <8>;
+	non-removable;
+	max-frequency = <200000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	status = "okay";
+};
+
+&spi3 {
+	pinctrl-0 = <&spi3m1_pins>;
+	status = "disabled";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "disabled";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-0 = <&uart7m1_xfer>;
+	status = "disabled";
+};
+
+&uart9 {
+	pinctrl-0 = <&uart9m1_xfer>;
+	status = "disabled";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};

files-6.1/scripts/bmpconvert

@@ -0,0 +1,313 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: GPL-2.0 */
+# -*- coding: utf-8 -*-
+
+from struct import unpack, pack
+import sys
+import getopt
+
+
+class BMPFile:
+
+    def __init__(self, file_path, force_revers=0, force_swap=0):
+        self.file = open(file_path, "rb+")
+        # bmp head 14bit
+        self.bfType = unpack("<h", self.file.read(2))[0]
+        self.bfSize = unpack("<i", self.file.read(4))[0]
+        self.bfReserved1 = unpack("<h", self.file.read(2))[0]
+        self.bfReserved2 = unpack("<h", self.file.read(2))[0]
+        self.bfOffBits = unpack("<i", self.file.read(4))[0]
+
+        self.biSize = unpack("<i", self.file.read(4))[0]
+        self.biWidth = unpack("<i", self.file.read(4))[0]
+        self.biHeight = unpack("<i", self.file.read(4))[0]
+        self.biPlanes = unpack("<h", self.file.read(2))[0]
+        self.biBitCount = unpack("<h", self.file.read(2))[0]
+        # bmp parameter 40 bit normaally
+        self.biCompression = unpack("<i", self.file.read(4))[0]
+        self.biSizeImage = unpack("<i", self.file.read(4))[0]
+        self.biXPixelsPerMeter = unpack("<i", self.file.read(4))[0]
+        self.biYPixelsPerMeter = unpack("<i", self.file.read(4))[0]
+        self.biClrUsed = unpack("<i", self.file.read(4))[0]
+        self.biClrImportant = unpack("<i", self.file.read(4))[0]
+        self.head = []
+        self.color_map = []
+        self.bmp_data = []
+        self.bf_map = []
+        self.force_revers = force_revers
+        self.force_swap = force_swap
+        # some software change parameter size more than 40 bit
+        if self.biSize > 40:
+            self.read_other(self.biSize-40)
+
+        if self.biBitCount == 16 and self.biCompression == 3:
+            for i in range(4):
+                self.bf_map.append(
+                    [unpack("<i", self.file.read(4))[0]]
+                )
+        if self.biBitCount == 24:
+            self.get_24bit_data()
+        elif self.biBitCount == 16:
+            if self.biCompression == 3:
+                self.bmp16bit_to_24bit_bf()
+            else:
+                self.bmp16bit_to_24bit()
+        elif self.biBitCount == 8:
+                # Not convert 8bit bmp logo to 24 bit
+                self.file.close()
+                return
+        else:
+            self.bmp32bit_to_24bit()
+        self.rb_swap = 0
+        if self.bfReserved1 != 8399 and self.biHeight > 0:
+            self.reverse_bmp_data()
+            print("reverse data at first time")
+        if self.force_revers:
+            self.reverse_bmp_data()
+            print("reverse data by force")
+        if self.force_swap:
+            self.rb_swap = 1
+            print("swap rb by force'")
+
+        if self.bfReserved1 == 8399:
+            self.file.close()
+            return
+
+        self.write_24bit(self.rb_swap)
+        self.file.close()
+
+    def read_other(self, n):
+        for i in range(n):
+            self.file.read(1)
+
+    def reverse_bmp_data(self):
+        self.bmp_data.reverse()
+
+    @staticmethod
+    def get_16bit_bgr_bf(pixel):
+        red = (pixel[1] & 0xf8) << 0
+        green = ((pixel[1] & 0x07) << 5) | ((pixel[0] & 0xe0) >> 3)
+        blue = ((pixel[0] & 0x1f) << 3)
+        new_pixel = [blue, green, red]
+        return new_pixel
+
+    def bmp32bit_to_24bit(self):
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            # bmp file 4 align
+            count = 0
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    [unpack("<B", self.file.read(1))[0], unpack("<B", self.file.read(1))[0], unpack("<B", self.file.read(1))[0]])
+                self.file.read(1)
+                count = count + 4
+            while count % 4 != 0:
+                self.file.read(1)
+                count = count + 1
+            self.bmp_data.append(bmp_data_row)
+
+    def bmp16bit_to_24bit_bf(self):
+        self.get_16bit_data()
+        temp_data = self.bmp_data
+        self.bmp_data = []
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    self.get_16bit_bgr_bf(temp_data[height][width])
+                )
+            self.bmp_data.append(bmp_data_row)
+
+    def bmp8bit_to_24bit_rle(self):
+        bmp_data_row = []
+        data_x = []
+        t_count = 0
+        loop = 1
+        while loop:
+            data1 = unpack("<B", self.file.read(1))[0]
+            if data1 > 0:
+                data2 = unpack("<B", self.file.read(1))[0]
+                for n in range(data1):
+                    bmp_data_row.append(self.color_map[data2])
+            if data1 == 0:
+                data2 = unpack("<B", self.file.read(1))[0]
+                if data2 > 2:
+                    data_count = data2
+                    data_temp = unpack("<B", self.file.read(1))[0]
+                    data_x.append(data_temp)
+                    while data_temp != 0:
+                        data_temp = unpack("<B", self.file.read(1))[0]
+                        data_x.append(data_temp)
+                    for m in range(data_count):
+                        bmp_data_row.append(self.color_map[data_x[m]])
+                if data2 == 2:
+                    print("data2 == 2")
+                if data2 == 0:
+                    t_count += 1
+                    self.bmp_data.append(bmp_data_row)
+                    bmp_data_row = []
+                if data2 == 1:
+                    print("encode over!")
+                    loop = 0
+
+    def bmp8bit_to_24bit(self):
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            count = 0
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    self.color_map[unpack("<B", self.file.read(1))[0]])
+                count = count + 1
+            while count % 4 != 0:
+                self.file.read(1)
+                count = count + 1
+            self.bmp_data.append(bmp_data_row)
+
+    @staticmethod
+    def get_16bit_bgr(pixel):
+        red = (pixel[1] & 0x7c) << 1
+        green = ((pixel[1] & 0x03) << 6) | ((pixel[0] & 0xe0) >> 2)
+        blue = ((pixel[0] & 0x1f) << 3)
+        new_pixel = [blue, green, red]
+        return new_pixel
+
+    def bmp16bit_to_24bit(self):
+        self.get_16bit_data()
+        temp_data = self.bmp_data
+        self.bmp_data = []
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    self.get_16bit_bgr(temp_data[height][width])
+                )
+            self.bmp_data.append(bmp_data_row)
+
+    def get_head(self):
+        self.file.seek(0, 0)
+        for i in range(54):
+            self.head.append(unpack("<B", self.file.read(1))[0])
+        return self.head
+
+    def get_16bit_data(self):
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            count = 0
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    [unpack("<B", self.file.read(1))[0], unpack("<B", self.file.read(1))[0]])
+                count = count + 2
+            while count % 4 != 0:
+                self.file.read(1)
+                count = count + 1
+            self.bmp_data.append(bmp_data_row)
+
+    def get_24bit_data(self):
+        for height in range(abs(self.biHeight)):
+            bmp_data_row = []
+            count = 0
+            for width in range(self.biWidth):
+                bmp_data_row.append(
+                    [unpack("<B", self.file.read(1))[0], unpack("<B", self.file.read(1))[0], unpack("<B", self.file.read(1))[0]])
+                count = count + 3
+            while count % 4 != 0:
+                self.file.read(1)
+                count = count + 1
+            self.bmp_data.append(bmp_data_row)
+
+    def write_24bit(self,rb_swap):
+        self.file.seek(0, 0)
+        self.write_head_24bit()
+        self.write_data_24bit(rb_swap)
+
+    def write_head(self):
+        self.file.write(pack("<h", self.bfType))
+        self.file.write(pack("<i", self.bfSize))
+        self.file.write(pack("<h", self.bfReserved1))
+        self.file.write(pack("<h", self.bfReserved2))
+        self.file.write(pack("<i", self.bfOffBits))  # bfOffBits
+        self.file.write(pack("<i", self.biSize))  # biSize
+        self.file.write(pack("<i", self.biWidth))
+
+        self.file.write(pack("<i", self.biHeight))
+        self.file.write(pack("<h", self.biPlanes))
+        self.file.write(pack("<h", self.biBitCount))  # biBitCount
+        self.file.write(pack("<i", self.biCompression))  # biCompression
+        self.file.write(pack("<i", self.biSizeImage))  # biSizeImage
+        self.file.write(pack("<i", self.biXPixelsPerMeter))  # biXPixelsPerMeter
+        self.file.write(pack("<i", self.biYPixelsPerMeter))  # biYPixelsPerMeter
+        self.file.write(pack("<i", self.biClrUsed))  # biClrUsed
+        self.file.write(pack("<i", self.biClrImportant))  # biClrImportant try to mark whether is reversed
+
+    def write_head_24bit(self):
+        temp_bi_width = self.biWidth * 3
+        while temp_bi_width % 4 != 0:
+            temp_bi_width = temp_bi_width + 1
+        new_bf_size = temp_bi_width * abs(self.biHeight) + 54
+        self.file.write(pack("<h", self.bfType))
+        self.file.write(pack("<i", new_bf_size))
+        self.file.write(pack("<h", 8399)) # a mark for uboot dealing
+        self.file.write(pack("<h", self.bfReserved2))
+        self.file.write(pack("<i", 54))  # bfOffBits
+        self.file.write(pack("<i", 40))  # biSize
+        self.file.write(pack("<i", self.biWidth))
+        # force height to negative let logo show normal in windows
+        # the uboot code can deal with negative height
+        if self.biHeight < 0:
+            self.file.write(pack("<i", self.biHeight))
+        else:
+            self.file.write(pack("<i", self.biHeight * -1))
+        self.file.write(pack("<h", self.biPlanes))
+        self.file.write(pack("<h", 24))  # biBitCount
+        self.file.write(pack("<i", 0))  # biCompression
+        self.file.write(pack("<i", 0))  # biSizeImage
+        self.file.write(pack("<i", 0))  # biXPixelsPerMeter
+        self.file.write(pack("<i", 0))  # biYPixelsPerMeter
+        self.file.write(pack("<i", 0))  # biClrUsed
+        self.file.write(pack("<i", 0))  # biClrImportant try to mark whether is reversed
+
+    def write_data_24bit(self, rb_swap):
+        for hg in range(abs(self.biHeight)):
+            count = 0
+            for wd in range(self.biWidth):
+                if rb_swap:
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][2]))
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][1]))
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][0]))
+                else:
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][0]))
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][1]))
+                    self.file.write(pack("<B", self.bmp_data[hg][wd][2]))
+                count = count + 3
+            while count % 4 != 0:
+                self.file.write(pack("<B", 0))
+                count = count + 1
+
+
+if __name__ == "__main__":
+
+    swap = 0
+    revers = 0
+    par = len(sys.argv[1:])
+    if par == 1:
+        bmp = BMPFile(sys.argv[1])
+    elif par == 0:
+        print("This program is trying to convert different format of bmpfile to a same format"
+                "to make vop can handle bmpfile easily")
+        print("try such cmd to make it work python bmpconvert xxx/xxx.bmp")
+    else:
+        try:
+            opts, args = getopt.getopt(sys.argv[2:], "hrs", ["help", "reverse", "swap"])
+            for opt, arg in opts:
+
+                if opt in ('-h','--help'):
+                    print("add -r option will force program to reverse data")
+                    print("add -s option will force program to swap data of rb")
+                if opt in ("-r", "--reverse"):
+                    revers = 1
+                if opt in ("-s", "--swap"):
+                    swap = 1
+            bmp = BMPFile(sys.argv[1], revers, swap)
+        except getopt.GetoptError:
+            sys.exit(1)
+

files-6.1/scripts/mkbootimg

@@ -0,0 +1,316 @@
+#!/usr/bin/env python
+# Copyright 2015, The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+from __future__ import print_function
+
+from argparse import ArgumentParser, FileType, Action
+from hashlib import sha1
+from os import fstat
+import re
+from struct import pack
+
+
+BOOT_IMAGE_HEADER_V3_PAGESIZE = 4096
+
+def filesize(f):
+    if f is None:
+        return 0
+    try:
+        return fstat(f.fileno()).st_size
+    except OSError:
+        return 0
+
+
+def update_sha(sha, f):
+    if f:
+        sha.update(f.read())
+        f.seek(0)
+        sha.update(pack('I', filesize(f)))
+    else:
+        sha.update(pack('I', 0))
+
+
+def pad_file(f, padding):
+    pad = (padding - (f.tell() & (padding - 1))) & (padding - 1)
+    f.write(pack(str(pad) + 'x'))
+
+
+def get_number_of_pages(image_size, page_size):
+    """calculates the number of pages required for the image"""
+    return (image_size + page_size - 1) / page_size
+
+
+def get_recovery_dtbo_offset(args):
+    """calculates the offset of recovery_dtbo image in the boot image"""
+    num_header_pages = 1 # header occupies a page
+    num_kernel_pages = get_number_of_pages(filesize(args.kernel), args.pagesize)
+    num_ramdisk_pages = get_number_of_pages(filesize(args.ramdisk), args.pagesize)
+    num_second_pages = get_number_of_pages(filesize(args.second), args.pagesize)
+    dtbo_offset = args.pagesize * (num_header_pages + num_kernel_pages +
+                                   num_ramdisk_pages + num_second_pages)
+    return dtbo_offset
+
+
+def write_header_v3(args):
+    BOOT_IMAGE_HEADER_V3_SIZE = 1580
+    BOOT_MAGIC = 'ANDROID!'.encode()
+
+    args.output.write(pack('8s', BOOT_MAGIC))
+    args.output.write(pack(
+        '4I',
+        filesize(args.kernel),                          # kernel size in bytes
+        filesize(args.ramdisk),                         # ramdisk size in bytes
+        (args.os_version << 11) | args.os_patch_level,  # os version and patch level
+        BOOT_IMAGE_HEADER_V3_SIZE))
+
+    args.output.write(pack('4I', 0, 0, 0, 0))           # reserved
+
+    args.output.write(pack('I', args.header_version))   # version of bootimage header
+    args.output.write(pack('1536s', args.cmdline.encode()))
+    pad_file(args.output, BOOT_IMAGE_HEADER_V3_PAGESIZE)
+
+def write_vendor_boot_header(args):
+    VENDOR_BOOT_IMAGE_HEADER_V3_SIZE = 2112
+    BOOT_MAGIC = 'VNDRBOOT'.encode()
+
+    args.vendor_boot.write(pack('8s', BOOT_MAGIC))
+    args.vendor_boot.write(pack(
+        '5I',
+        args.header_version,                            # version of header
+        args.pagesize,                                  # flash page size we assume
+        args.base + args.kernel_offset,                 # kernel physical load addr
+        args.base + args.ramdisk_offset,                # ramdisk physical load addr
+        filesize(args.vendor_ramdisk)))                 # vendor ramdisk size in bytes
+    args.vendor_boot.write(pack('2048s', args.vendor_cmdline.encode()))
+    args.vendor_boot.write(pack('I', args.base + args.tags_offset)) # physical addr for kernel tags
+    args.vendor_boot.write(pack('16s', args.board.encode())) # asciiz product name
+    args.vendor_boot.write(pack('I', VENDOR_BOOT_IMAGE_HEADER_V3_SIZE)) # header size in bytes
+    if filesize(args.dtb) == 0:
+        raise ValueError("DTB image must not be empty.")
+    args.vendor_boot.write(pack('I', filesize(args.dtb)))   # size in bytes
+    args.vendor_boot.write(pack('Q', args.base + args.dtb_offset)) # dtb physical load address
+    pad_file(args.vendor_boot, args.pagesize)
+
+def write_header(args):
+    BOOT_IMAGE_HEADER_V1_SIZE = 1648
+    BOOT_IMAGE_HEADER_V2_SIZE = 1660
+    BOOT_MAGIC = 'ANDROID!'.encode()
+
+    if args.header_version > 3:
+        raise ValueError('Boot header version %d not supported' % args.header_version)
+    elif args.header_version == 3:
+        return write_header_v3(args)
+
+    args.output.write(pack('8s', BOOT_MAGIC))
+    final_ramdisk_offset = (args.base + args.ramdisk_offset) if filesize(args.ramdisk) > 0 else 0
+    final_second_offset = (args.base + args.second_offset) if filesize(args.second) > 0 else 0
+    args.output.write(pack(
+        '10I',
+        filesize(args.kernel),                          # size in bytes
+        args.base + args.kernel_offset,                 # physical load addr
+        filesize(args.ramdisk),                         # size in bytes
+        final_ramdisk_offset,                           # physical load addr
+        filesize(args.second),                          # size in bytes
+        final_second_offset,                            # physical load addr
+        args.base + args.tags_offset,                   # physical addr for kernel tags
+        args.pagesize,                                  # flash page size we assume
+        args.header_version,                            # version of bootimage header
+        (args.os_version << 11) | args.os_patch_level)) # os version and patch level
+    args.output.write(pack('16s', args.board.encode())) # asciiz product name
+    args.output.write(pack('512s', args.cmdline[:512].encode()))
+
+    sha = sha1()
+    update_sha(sha, args.kernel)
+    update_sha(sha, args.ramdisk)
+    update_sha(sha, args.second)
+
+    if args.header_version > 0:
+        update_sha(sha, args.recovery_dtbo)
+    if args.header_version > 1:
+        update_sha(sha, args.dtb)
+
+    img_id = pack('32s', sha.digest())
+
+    args.output.write(img_id)
+    args.output.write(pack('1024s', args.cmdline[512:].encode()))
+
+    if args.header_version > 0:
+        args.output.write(pack('I', filesize(args.recovery_dtbo)))   # size in bytes
+        if args.recovery_dtbo:
+            args.output.write(pack('Q', get_recovery_dtbo_offset(args))) # recovery dtbo offset
+        else:
+            args.output.write(pack('Q', 0)) # Will be set to 0 for devices without a recovery dtbo
+
+    # Populate boot image header size for header versions 1 and 2.
+    if args.header_version == 1:
+        args.output.write(pack('I', BOOT_IMAGE_HEADER_V1_SIZE))
+    elif args.header_version == 2:
+        args.output.write(pack('I', BOOT_IMAGE_HEADER_V2_SIZE))
+
+    if args.header_version > 1:
+
+        # if filesize(args.dtb) == 0:
+        #     raise ValueError("DTB image must not be empty.")
+
+        args.output.write(pack('I', filesize(args.dtb)))   # size in bytes
+        args.output.write(pack('Q', args.base + args.dtb_offset)) # dtb physical load address
+    pad_file(args.output, args.pagesize)
+    return img_id
+
+
+class ValidateStrLenAction(Action):
+    def __init__(self, option_strings, dest, nargs=None, **kwargs):
+        if 'maxlen' not in kwargs:
+            raise ValueError('maxlen must be set')
+        self.maxlen = int(kwargs['maxlen'])
+        del kwargs['maxlen']
+        super(ValidateStrLenAction, self).__init__(option_strings, dest, **kwargs)
+
+    def __call__(self, parser, namespace, values, option_string=None):
+        if len(values) > self.maxlen:
+            raise ValueError(
+                'String argument too long: max {0:d}, got {1:d}'.format(self.maxlen, len(values)))
+        setattr(namespace, self.dest, values)
+
+
+def write_padded_file(f_out, f_in, padding):
+    if f_in is None:
+        return
+    f_out.write(f_in.read())
+    pad_file(f_out, padding)
+
+
+def parse_int(x):
+    return int(x, 0)
+
+
+def parse_os_version(x):
+    match = re.search(r'^(\d{1,3})(?:\.(\d{1,3})(?:\.(\d{1,3}))?)?', x)
+    if match:
+        a = int(match.group(1))
+        b = c = 0
+        if match.lastindex >= 2:
+            b = int(match.group(2))
+        if match.lastindex == 3:
+            c = int(match.group(3))
+        # 7 bits allocated for each field
+        assert a < 128
+        assert b < 128
+        assert c < 128
+        return (a << 14) | (b << 7) | c
+    return 0
+
+
+def parse_os_patch_level(x):
+    match = re.search(r'^(\d{4})-(\d{2})(?:-(\d{2}))?', x)
+    if match:
+        y = int(match.group(1)) - 2000
+        m = int(match.group(2))
+        # 7 bits allocated for the year, 4 bits for the month
+        assert 0 <= y < 128
+        assert 0 < m <= 12
+        return (y << 4) | m
+    return 0
+
+
+def parse_cmdline():
+    parser = ArgumentParser()
+    parser.add_argument('--kernel', help='path to the kernel', type=FileType('rb'))
+    parser.add_argument('--ramdisk', help='path to the ramdisk', type=FileType('rb'))
+    parser.add_argument('--second', help='path to the 2nd bootloader', type=FileType('rb'))
+    parser.add_argument('--dtb', help='path to dtb', type=FileType('rb'))
+    recovery_dtbo_group = parser.add_mutually_exclusive_group()
+    recovery_dtbo_group.add_argument('--recovery_dtbo', help='path to the recovery DTBO',
+                                     type=FileType('rb'))
+    recovery_dtbo_group.add_argument('--recovery_acpio', help='path to the recovery ACPIO',
+                                     type=FileType('rb'), metavar='RECOVERY_ACPIO',
+                                     dest='recovery_dtbo')
+    parser.add_argument('--cmdline', help='extra arguments to be passed on the '
+                        'kernel command line', default='', action=ValidateStrLenAction, maxlen=1536)
+    parser.add_argument('--vendor_cmdline',
+                        help='kernel command line arguments contained in vendor boot',
+                        default='', action=ValidateStrLenAction, maxlen=2048)
+    parser.add_argument('--base', help='base address', type=parse_int, default=0x10000000)
+    parser.add_argument('--kernel_offset', help='kernel offset', type=parse_int, default=0x00008000)
+    parser.add_argument('--ramdisk_offset', help='ramdisk offset', type=parse_int,
+                        default=0x01000000)
+    parser.add_argument('--second_offset', help='2nd bootloader offset', type=parse_int,
+                        default=0x00f00000)
+    parser.add_argument('--dtb_offset', help='dtb offset', type=parse_int, default=0x01f00000)
+
+    parser.add_argument('--os_version', help='operating system version', type=parse_os_version,
+                        default=0)
+    parser.add_argument('--os_patch_level', help='operating system patch level',
+                        type=parse_os_patch_level, default=0)
+    parser.add_argument('--tags_offset', help='tags offset', type=parse_int, default=0x00000100)
+    parser.add_argument('--board', help='board name', default='', action=ValidateStrLenAction,
+                        maxlen=16)
+    parser.add_argument('--pagesize', help='page size', type=parse_int,
+                        choices=[2**i for i in range(11, 15)], default=2048)
+    parser.add_argument('--id', help='print the image ID on standard output',
+                        action='store_true')
+    parser.add_argument('--header_version', help='boot image header version', type=parse_int,
+                        default=0)
+    parser.add_argument('-o', '--output', help='output file name', type=FileType('wb'))
+    parser.add_argument('--vendor_boot', help='vendor boot output file name', type=FileType('wb'))
+    parser.add_argument('--vendor_ramdisk', help='path to the vendor ramdisk', type=FileType('rb'))
+
+    return parser.parse_args()
+
+
+def write_data(args, pagesize):
+    write_padded_file(args.output, args.kernel, pagesize)
+    write_padded_file(args.output, args.ramdisk, pagesize)
+    write_padded_file(args.output, args.second, pagesize)
+
+    if args.header_version > 0 and args.header_version < 3:
+        write_padded_file(args.output, args.recovery_dtbo, pagesize)
+    if args.header_version == 2:
+        write_padded_file(args.output, args.dtb, pagesize)
+
+
+def write_vendor_boot_data(args):
+    write_padded_file(args.vendor_boot, args.vendor_ramdisk, args.pagesize)
+    write_padded_file(args.vendor_boot, args.dtb, args.pagesize)
+
+
+def main():
+    args = parse_cmdline()
+    if args.vendor_boot is not None:
+        if args.header_version < 3:
+            raise ValueError('--vendor_boot not compatible with given header version')
+        if args.vendor_ramdisk is None:
+            raise ValueError('--vendor_ramdisk missing or invalid')
+        write_vendor_boot_header(args)
+        write_vendor_boot_data(args)
+    if args.output is not None:
+        if args.kernel is None:
+            raise ValueError('kernel must be supplied when creating a boot image')
+        if args.second is not None and args.header_version > 2:
+            raise ValueError('--second not compatible with given header version')
+        img_id = write_header(args)
+        if args.header_version > 2:
+            write_data(args, BOOT_IMAGE_HEADER_V3_PAGESIZE)
+        else:
+            write_data(args, args.pagesize)
+        if args.id and img_id is not None:
+            # Python 2's struct.pack returns a string, but py3 returns bytes.
+            if isinstance(img_id, str):
+                img_id = [ord(x) for x in img_id]
+            print('0x' + ''.join('{:02x}'.format(c) for c in img_id))
+
+
+if __name__ == '__main__':
+    main()

files-6.1/scripts/mkimg

@@ -0,0 +1,263 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+
+set -e
+
+usage() {
+	cat >&2 << USAGE
+usage: $0 [-h] --dtb DTB
+
+optional arguments:
+  -h, --help            show this help message and exit
+  --dtb DTB             the dtb file name
+USAGE
+}
+
+# Parse command-line arguments
+while [ $# -gt 0 ]; do
+	case $1 in
+		--dtb)
+			DTB=$2
+			shift 2
+			;;
+		--keep-dtb-name)
+			DTB_ARGS="--dtbname"; shift 1;;
+		-h)
+			usage
+			exit 0
+			;;
+		--help)
+			usage
+			exit 0
+			;;
+		*)
+			shift
+			;;
+        esac
+done
+
+srctree=${srctree-"."}
+objtree=${objtree-"."}
+if [ "${ARCH}" == "" ]; then
+	if [ "$($srctree/scripts/config --state CONFIG_ARM)" == "y" ]; then
+		ARCH=arm
+	else
+		ARCH=arm64
+	fi
+fi
+
+LOGO_PATH=${srctree}/logo.bmp
+[ -f ${LOGO_PATH} ] && LOGO=logo.bmp
+
+LOGO_KERNEL_PATH=${srctree}/logo_kernel.bmp
+[ -f ${LOGO_KERNEL_PATH} ] && LOGO_KERNEL=logo_kernel.bmp
+
+KERNEL_IMAGE_PATH=${objtree}/arch/${ARCH}/boot/Image
+KERNEL_IMAGE_ARG="--kernel ${KERNEL_IMAGE_PATH}"
+if [ "${ARCH}" == "arm" ]; then
+	DTB_PATH=${objtree}/arch/arm/boot/dts/${DTB}
+	ZIMAGE=zImage
+else
+	DTB_PATH=${objtree}/arch/arm64/boot/dts/rockchip/${DTB}
+	ZIMAGE=Image.lz4
+fi
+KERNEL_ZIMAGE_PATH=${objtree}/arch/${ARCH}/boot/${ZIMAGE}
+KERNEL_ZIMAGE_ARG="--kernel ${KERNEL_ZIMAGE_PATH}"
+if ! find ${DTB_PATH} >/dev/null; then
+	echo "No dtb" >&2
+	usage
+	exit 1
+fi
+
+OUT=out
+ITB=${BOOT_IMG}
+ITS=${OUT}/boot.its
+MKIMAGE=${MKIMAGE-"mkimage"}
+MKIMAGE_ARG="-E -p 0x800"
+
+make_boot_img()
+{
+	RAMDISK_IMG_PATH=${objtree}/ramdisk.img
+	[ -f ${RAMDISK_IMG_PATH} ] && RAMDISK_IMG=ramdisk.img && RAMDISK_ARG="--ramdisk ${RAMDISK_IMG_PATH}"
+
+	${srctree}/scripts/mkbootimg \
+		${KERNEL_IMAGE_ARG} \
+		${RAMDISK_ARG} \
+		--second resource.img \
+		-o boot.img && \
+	echo "  Image:  boot.img (with Image ${RAMDISK_IMG} resource.img) is ready";
+	[ -f ${KERNEL_ZIMAGE_PATH} ] || return 0
+	${srctree}/scripts/mkbootimg \
+		${KERNEL_ZIMAGE_ARG} \
+		${RAMDISK_ARG} \
+		--second resource.img \
+		-o zboot.img && \
+	echo "  Image:  zboot.img (with ${ZIMAGE} ${RAMDISK_IMG} resource.img) is ready"
+}
+
+repack_boot_img()
+{
+	${srctree}/scripts/repack-bootimg \
+		--boot_img ${BOOT_IMG} --out ${OUT} \
+		${KERNEL_IMAGE_ARG} \
+		--second resource.img \
+		--dtb ${DTB_PATH} \
+		-o boot.img &&
+	echo "  Image:  boot.img (${BOOT_IMG} + Image) is ready";
+	${srctree}/scripts/repack-bootimg \
+		--boot_img ${BOOT_IMG} --out ${OUT} \
+		${KERNEL_ZIMAGE_ARG} \
+		--second resource.img \
+		--dtb ${DTB_PATH} \
+		-o zboot.img && \
+	echo "  Image:  zboot.img (${BOOT_IMG} + ${ZIMAGE}) is ready"
+}
+
+check_mkimage()
+{
+	MKIMAGE=$(type -p ${MKIMAGE} || true)
+	if [ -z "${MKIMAGE}" ]; then
+		# Doesn't exist
+		echo '"mkimage" command not found - U-Boot images will not be built' >&2
+		exit 1;
+	fi
+}
+
+unpack_itb()
+{
+	rm -rf ${OUT}
+	mkdir -p ${OUT}
+
+	for NAME in $(fdtget -l ${ITB} /images)
+	do
+		# generate image
+		NODE="/images/${NAME}"
+		OFFS=$(fdtget -ti ${ITB} ${NODE} data-position)
+		SIZE=$(fdtget -ti ${ITB} ${NODE} data-size)
+		if [ -z ${OFFS} ]; then
+			continue;
+		fi
+
+		if [ ${SIZE} -ne 0 ]; then
+			dd if=${ITB} of=${OUT}/${NAME} bs=${SIZE} count=1 skip=${OFFS} iflag=skip_bytes >/dev/null 2>&1
+		else
+			touch ${OUT}/${NAME}
+		fi
+	done
+
+	[ ! -f ${OUT}/kernel ] && echo "FIT ${ITB} no kernel" >&2 && exit 1 || true
+}
+
+gen_its()
+{
+	TMP_ITB=${OUT}/boot.tmp
+
+	# add placeholder
+	cp ${ITB} ${TMP_ITB}
+	for NAME in $(fdtget -l ${ITB} /images); do
+		fdtput -t s ${TMP_ITB} /images/${NAME} data "/INCBIN/(${NAME})"
+	done
+	dtc -I dtb -O dts ${TMP_ITB} -o ${ITS} >/dev/null 2>&1
+	rm -f ${TMP_ITB}
+
+	# fixup placeholder: data = "/INCBIN/(...)"; -> data = /incbin/("...");
+	sed -i "s/\"\/INCBIN\/(\(.*\))\"/\/incbin\/(\"\1\")/" ${ITS}
+
+	# remove
+	sed -i "/memreserve/d"		${ITS}
+	sed -i "/timestamp/d"		${ITS}
+	sed -i "/data-size/d"		${ITS}
+	sed -i "/data-position/d"	${ITS}
+	sed -i "/value/d"		${ITS}
+	sed -i "/hashed-strings/d"	${ITS}
+	sed -i "/hashed-nodes/d"	${ITS}
+	sed -i "/signer-version/d"	${ITS}
+	sed -i "/signer-name/d"		${ITS}
+}
+
+gen_itb()
+{
+	[ -f ${OUT}/fdt ] && cp -a ${DTB_PATH} ${OUT}/fdt && FDT=" + ${DTB}"
+	[ -f ${OUT}/resource ] && cp -a resource.img ${OUT}/resource && RESOURCE=" + resource.img"
+	COMP=$(fdtget ${ITB} /images/kernel compression)
+	case "${COMP}" in
+		gzip)	EXT=".gz";;
+		lz4)	EXT=".lz4";;
+		bzip2)	EXT=".bz2";;
+		lzma)	EXT=".lzma";;
+		lzo)	EXT=".lzo";;
+	esac
+	cp -a ${KERNEL_IMAGE_PATH}${EXT} ${OUT}/kernel && \
+	${MKIMAGE} ${MKIMAGE_ARG} -f ${ITS} boot.img >/dev/null && \
+	echo "  Image:  boot.img (FIT ${BOOT_IMG} + Image${EXT}${FDT}${RESOURCE}) is ready";
+	if [ "${EXT}" == "" ] && [ -f ${KERNEL_ZIMAGE_PATH} ]; then
+		cp -a ${KERNEL_ZIMAGE_PATH} ${OUT}/kernel && \
+		${MKIMAGE} ${MKIMAGE_ARG} -f ${ITS} zboot.img >/dev/null && \
+		echo "  Image:  zboot.img (FIT ${BOOT_IMG} + zImage${FDT}${RESOURCE}) is ready";
+	fi
+}
+
+repack_itb()
+{
+	check_mkimage
+	unpack_itb
+	gen_its
+	gen_itb
+}
+
+# Create U-Boot FIT Image use ${BOOT_ITS}
+make_fit_boot_img()
+{
+	ITS=${OUT}/boot.its
+
+	check_mkimage
+	mkdir -p ${OUT}
+	rm -f ${OUT}/fdt ${OUT}/kernel ${OUT}/resource ${ITS}
+
+	cp -a ${BOOT_ITS} ${ITS}
+	cp -a ${DTB_PATH} ${OUT}/fdt
+	cp -a ${KERNEL_ZIMAGE_PATH} ${OUT}/kernel
+	cp -a resource.img ${OUT}/resource
+
+	if [ "${ARCH}" == "arm64" ]; then
+		sed -i -e 's/arch = ""/arch = "arm64"/g' -e 's/compression = ""/compression = "lz4"/' ${ITS}
+	else
+		sed -i -e 's/arch = ""/arch = "arm"/g' -e 's/compression = ""/compression = "none"/' ${ITS}
+	fi
+	FIT_DESC=$(${MKIMAGE} ${MKIMAGE_ARG} -f ${ITS} boot.img | grep "FIT description" | sed 's/FIT description: //')
+	echo "  Image:  boot.img (${FIT_DESC}) is ready";
+}
+
+if [ -x ${srctree}/scripts/bmpconvert ]; then
+	if [ -f ${LOGO_PATH} ]; then
+		${srctree}/scripts/bmpconvert ${LOGO_PATH};
+	fi
+	if [ -f ${LOGO_KERNEL_PATH} ]; then
+		${srctree}/scripts/bmpconvert ${LOGO_KERNEL_PATH};
+	fi
+fi
+
+if [ "${srctree}" != "${objtree}" ]; then
+	if [ -f ${LOGO_PATH} ]; then
+		cp -a ${LOGO_PATH} ${objtree}/;
+	fi
+	if [ -f ${LOGO_KERNEL_PATH} ]; then
+		cp -a ${LOGO_KERNEL_PATH} ${objtree}/;
+	fi
+fi
+
+scripts/resource_tool ${DTB_ARGS} ${DTB_PATH} ${LOGO} ${LOGO_KERNEL} >/dev/null
+echo "  Image:  resource.img (with ${DTB} ${LOGO} ${LOGO_KERNEL}) is ready"
+
+if [ -f "${BOOT_IMG}" ]; then
+	if file -L -p -b ${BOOT_IMG} | grep -q 'Device Tree Blob' ; then
+		repack_itb;
+	elif [ -x ${srctree}/scripts/repack-bootimg ]; then
+		repack_boot_img;
+	fi
+elif [ -f "${BOOT_ITS}" ]; then
+	make_fit_boot_img;
+elif [ -x ${srctree}/scripts/mkbootimg ]; then
+	make_boot_img;
+fi

files-6.1/scripts/mkkrnlimg.c

@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+//#define DEBUG
+#ifdef DEBUG
+#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+static inline __attribute__ ((format(printf, 1, 2)))
+int PRINTF(const char *fmt, ...)
+{
+	return 0;
+}
+#endif
+
+static uint32_t gTable_Crc32[256] = {
+	0x00000000, 0x04c10db7, 0x09821b6e, 0x0d4316d9,
+	0x130436dc, 0x17c53b6b, 0x1a862db2, 0x1e472005,
+	0x26086db8, 0x22c9600f, 0x2f8a76d6, 0x2b4b7b61,
+	0x350c5b64, 0x31cd56d3, 0x3c8e400a, 0x384f4dbd,
+	0x4c10db70, 0x48d1d6c7, 0x4592c01e, 0x4153cda9,
+	0x5f14edac, 0x5bd5e01b, 0x5696f6c2, 0x5257fb75,
+	0x6a18b6c8, 0x6ed9bb7f, 0x639aada6, 0x675ba011,
+	0x791c8014, 0x7ddd8da3, 0x709e9b7a, 0x745f96cd,
+	0x9821b6e0, 0x9ce0bb57, 0x91a3ad8e, 0x9562a039,
+	0x8b25803c, 0x8fe48d8b, 0x82a79b52, 0x866696e5,
+	0xbe29db58, 0xbae8d6ef, 0xb7abc036, 0xb36acd81,
+	0xad2ded84, 0xa9ece033, 0xa4aff6ea, 0xa06efb5d,
+	0xd4316d90, 0xd0f06027, 0xddb376fe, 0xd9727b49,
+	0xc7355b4c, 0xc3f456fb, 0xceb74022, 0xca764d95,
+	0xf2390028, 0xf6f80d9f, 0xfbbb1b46, 0xff7a16f1,
+	0xe13d36f4, 0xe5fc3b43, 0xe8bf2d9a, 0xec7e202d,
+	0x34826077, 0x30436dc0, 0x3d007b19, 0x39c176ae,
+	0x278656ab, 0x23475b1c, 0x2e044dc5, 0x2ac54072,
+	0x128a0dcf, 0x164b0078, 0x1b0816a1, 0x1fc91b16,
+	0x018e3b13, 0x054f36a4, 0x080c207d, 0x0ccd2dca,
+	0x7892bb07, 0x7c53b6b0, 0x7110a069, 0x75d1adde,
+	0x6b968ddb, 0x6f57806c, 0x621496b5, 0x66d59b02,
+	0x5e9ad6bf, 0x5a5bdb08, 0x5718cdd1, 0x53d9c066,
+	0x4d9ee063, 0x495fedd4, 0x441cfb0d, 0x40ddf6ba,
+	0xaca3d697, 0xa862db20, 0xa521cdf9, 0xa1e0c04e,
+	0xbfa7e04b, 0xbb66edfc, 0xb625fb25, 0xb2e4f692,
+	0x8aabbb2f, 0x8e6ab698, 0x8329a041, 0x87e8adf6,
+	0x99af8df3, 0x9d6e8044, 0x902d969d, 0x94ec9b2a,
+	0xe0b30de7, 0xe4720050, 0xe9311689, 0xedf01b3e,
+	0xf3b73b3b, 0xf776368c, 0xfa352055, 0xfef42de2,
+	0xc6bb605f, 0xc27a6de8, 0xcf397b31, 0xcbf87686,
+	0xd5bf5683, 0xd17e5b34, 0xdc3d4ded, 0xd8fc405a,
+	0x6904c0ee, 0x6dc5cd59, 0x6086db80, 0x6447d637,
+	0x7a00f632, 0x7ec1fb85, 0x7382ed5c, 0x7743e0eb,
+	0x4f0cad56, 0x4bcda0e1, 0x468eb638, 0x424fbb8f,
+	0x5c089b8a, 0x58c9963d, 0x558a80e4, 0x514b8d53,
+	0x25141b9e, 0x21d51629, 0x2c9600f0, 0x28570d47,
+	0x36102d42, 0x32d120f5, 0x3f92362c, 0x3b533b9b,
+	0x031c7626, 0x07dd7b91, 0x0a9e6d48, 0x0e5f60ff,
+	0x101840fa, 0x14d94d4d, 0x199a5b94, 0x1d5b5623,
+	0xf125760e, 0xf5e47bb9, 0xf8a76d60, 0xfc6660d7,
+	0xe22140d2, 0xe6e04d65, 0xeba35bbc, 0xef62560b,
+	0xd72d1bb6, 0xd3ec1601, 0xdeaf00d8, 0xda6e0d6f,
+	0xc4292d6a, 0xc0e820dd, 0xcdab3604, 0xc96a3bb3,
+	0xbd35ad7e, 0xb9f4a0c9, 0xb4b7b610, 0xb076bba7,
+	0xae319ba2, 0xaaf09615, 0xa7b380cc, 0xa3728d7b,
+	0x9b3dc0c6, 0x9ffccd71, 0x92bfdba8, 0x967ed61f,
+	0x8839f61a, 0x8cf8fbad, 0x81bbed74, 0x857ae0c3,
+	0x5d86a099, 0x5947ad2e, 0x5404bbf7, 0x50c5b640,
+	0x4e829645, 0x4a439bf2, 0x47008d2b, 0x43c1809c,
+	0x7b8ecd21, 0x7f4fc096, 0x720cd64f, 0x76cddbf8,
+	0x688afbfd, 0x6c4bf64a, 0x6108e093, 0x65c9ed24,
+	0x11967be9, 0x1557765e, 0x18146087, 0x1cd56d30,
+	0x02924d35, 0x06534082, 0x0b10565b, 0x0fd15bec,
+	0x379e1651, 0x335f1be6, 0x3e1c0d3f, 0x3add0088,
+	0x249a208d, 0x205b2d3a, 0x2d183be3, 0x29d93654,
+	0xc5a71679, 0xc1661bce, 0xcc250d17, 0xc8e400a0,
+	0xd6a320a5, 0xd2622d12, 0xdf213bcb, 0xdbe0367c,
+	0xe3af7bc1, 0xe76e7676, 0xea2d60af, 0xeeec6d18,
+	0xf0ab4d1d, 0xf46a40aa, 0xf9295673, 0xfde85bc4,
+	0x89b7cd09, 0x8d76c0be, 0x8035d667, 0x84f4dbd0,
+	0x9ab3fbd5, 0x9e72f662, 0x9331e0bb, 0x97f0ed0c,
+	0xafbfa0b1, 0xab7ead06, 0xa63dbbdf, 0xa2fcb668,
+	0xbcbb966d, 0xb87a9bda, 0xb5398d03, 0xb1f880b4,
+};
+
+static uint32_t CRC_32(uint8_t *aData, long aSize)
+{
+	long i;
+	uint32_t nAccum = 0;
+
+	for (i = 0; i < aSize; i++)
+		nAccum =
+		    (nAccum << 8) ^ gTable_Crc32[(nAccum >> 24) ^ *aData++];
+	return nAccum;
+}
+
+#define TAG_KERNEL 0x4C4E524B
+
+int main(int argc, char *argv[])
+{
+	FILE *fid_in, *fid_out;
+	size_t cnt;
+	uint8_t *ptr1;
+	long fileSize;
+	int exit_code = 0;
+	uint32_t crcData;
+
+	PRINTF("mkkrnlimg V20111117\n");
+	PRINTF("cmd:%s %s [%s]\n", argv[1], argv[2], argv[3]);
+	if (argc < 3) {
+		printf("Usage: %s srcFile desFile [flag]\n", argv[0]);
+		printf("sample:\n");
+		printf("         %s Image kernel.img\n", argv[0]);
+		exit(1);
+	}
+
+	fid_in = fopen(argv[1], "rb");
+	if (fid_in == 0) {
+		printf("input open NG !\n ");
+		exit(2);
+	}
+
+	fid_out = fopen(argv[2], "wb");
+	if (fid_out == 0) {
+		printf("output open NG !\n ");
+		fclose(fid_in);
+		exit(3);
+	}
+	fseek(fid_in, 0, SEEK_END);
+	fileSize = ftell(fid_in);
+	PRINTF("fileSize = %ld\n", fileSize);
+	fseek(fid_in, 0, SEEK_SET);
+	ptr1 = malloc(fileSize + 512 + 20);
+	if (ptr1 == 0) {
+		exit_code = 4;
+		printf("\n malloc error!");
+		goto app_exit;
+	}
+
+	*(uint32_t *)ptr1 = TAG_KERNEL;
+	*(uint32_t *)(ptr1 + 4) = fileSize;
+	fwrite(ptr1, 1, 8, fid_out);
+	cnt = fread(ptr1, 1, fileSize, fid_in);
+	PRINTF("fread = %lu\n", cnt);
+	crcData = CRC_32(ptr1, fileSize);
+	PRINTF("crc = 0x%x\n", crcData);
+	cnt = fwrite(ptr1, 1, fileSize, fid_out);
+	PRINTF("fwrite = %lu\n", cnt);
+	fwrite(&crcData, 1, 4, fid_out);
+
+app_exit:
+	fclose(fid_in);
+	fclose(fid_out);
+	if (ptr1)
+		free(ptr1);
+	exit(exit_code);
+}

files-6.1/scripts/repack-bootimg

@@ -0,0 +1,153 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+set -e
+
+usage() {
+	cat >&2 << USAGE
+usage: $0 [-h] [-z] --boot_img BOOT_IMG [--out OUT] [--kernel KERNEL] [--ramdisk RAMDISK] [--second SECOND] [--dtb DTB ] [--recovery_dtbo RECOVERY_DTBO] -o OUTPUT
+
+optional arguments:
+  -h, --help            show this help message and exit
+  -z                    pack compressed kernel image
+  --boot_img BOOT_IMG   path to the original boot image
+  --out OUT             path to out binaries (default: out)
+  --kernel KERNEL       path to the new kernel
+  --ramdisk RAMDISK     path to the new ramdisk
+  --second SECOND       path to the new 2nd bootloader (default: resource.img)
+  --dtb DTB             path to the new dtb
+  --recovery_dtbo RECOVERY_DTBO
+                        path to the new recovery DTBO
+  -o OUTPUT, --output OUTPUT
+                        output file name
+USAGE
+}
+
+# Parse command-line arguments
+while [ $# -gt 0 ]; do
+	case $1 in
+		--boot_img)
+			boot_img=$2
+			shift 2
+			;;
+		--out)
+			out=$2
+			shift 2
+			;;
+		--kernel)
+			kernel=$2
+			shift 2
+			;;
+		--ramdisk)
+			ramdisk=$2
+			shift 2
+			;;
+		--second)
+			second=$2
+			shift 2
+			;;
+		--dtb)
+			dtb=$2
+			shift 2
+			;;
+		--recovery_dtbo)
+			recovery_dtbo=$2
+			shift 2
+			;;
+		-h)
+			usage
+			exit 0
+			;;
+		--help)
+			usage
+			exit 0
+			;;
+		-z)
+			compressed_kernel=y
+			shift
+			;;
+		-o)
+			output=$2
+			shift 2
+			;;
+		--output)
+			output=$2
+			shift 2
+			;;
+		*)
+			shift
+			;;
+        esac
+done
+
+if [ "$boot_img" == "" -o ! -e "$boot_img" ]; then
+	echo "No boot img"
+	usage
+	exit 1
+fi
+
+if [ "$output" == "" ]; then
+	echo "No output file name"
+	usage
+	exit 1
+fi
+
+srctree=${srctree-"."}
+objtree=${objtree-"."}
+out=${out-"out"}
+if [ "$($srctree/scripts/config --state CONFIG_ARM64)" == "y" ]; then
+	if [ "$compressed_kernel" == "y" ]; then
+		default_kernel=arch/arm64/boot/Image.lz4
+	else
+		default_kernel=arch/arm64/boot/Image
+	fi
+else
+	if [ "$compressed_kernel" == "y" ]; then
+		default_kernel=arch/arm/boot/zImage
+	else
+		default_kernel=arch/arm/boot/Image
+	fi
+fi
+kernel=${kernel-$objtree/$default_kernel}
+second=${second-$objtree/resource.img}
+ramdisk=${ramdisk-$out/ramdisk}
+dtb=${dtb-$out/dtb}
+recovery_dtbo=${recovery_dtbo-$out/recovery_dtbo}
+log="$out/unpack.log"
+
+mkdir -p $out
+$srctree/scripts/unpack_bootimg --boot_img $boot_img --out $out > $log
+
+cmdline=$(grep -a "^command line args: " $log | tr '\0' '\n'| sed "s/^command line args: //")
+extra_cmdline=$(grep -a "^additional command line args: " $log | tr '\0' '\n'| sed "s/^additional command line args: //")
+version=$(grep -a "^boot image header version: " $log | sed "s/^boot image header version: //")
+os_version=$(grep -a "^os version: " $log | sed "s/^os version: //")
+os_patch_level=$(grep -a "^os patch level: " $log | sed "s/^os patch level: //")
+
+dtb_size=$(grep -a "^dtb size: " $log | sed "s/^dtb size: //")
+dtb_size=${dtb_size:-0}
+if [ $dtb_size -gt 0 -a -e "$dtb" ]; then
+	DTB="--dtb $dtb"
+fi
+
+recovery_dtbo_size=$(grep -a "^recovery dtbo size: " $log | sed "s/^recovery dtbo size: //")
+recovery_dtbo_size=${recovery_dtbo_size:-0}
+if [ $recovery_dtbo_size -gt 0 -a -e "$recovery_dtbo" ]; then
+	RECOVERY_DTBO="--recovery_dtbo $recovery_dtbo"
+fi
+
+if [ $version -lt 3 ]; then
+	SECOND="--second $second"
+fi
+
+$srctree/scripts/mkbootimg \
+--kernel $kernel \
+$SECOND \
+--ramdisk $ramdisk \
+$DTB \
+$RECOVERY_DTBO \
+--cmdline "${cmdline}${extra_cmdline}" \
+--header_version $version \
+--os_version $os_version \
+--os_patch_level $os_patch_level \
+--output $output

image/Makefile

@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+DEVICE_VARS += UBOOT_DEVICE_NAME
+
+define Build/Compile
+	$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux
+endef
+
+### Image scripts ###
+define Build/boot-common
+	# This creates a new folder copies the dtb (as rockchip.dtb) 
+	# and the kernel image (as kernel.img)
+	rm -fR $@.boot
+	mkdir -p $@.boot
+
+	$(CP) $(IMAGE_KERNEL) $@.boot/kernel.img
+endef
+
+define Build/boot-script
+	# Make an U-boot image and copy it to the boot partition
+	mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr
+endef
+
+define Build/pine64-img
+	# Creates the final SD/eMMC images, 
+	# combining boot partition, root partition as well as the u-boot bootloader
+
+	# Generate a new partition table in $@ with 32 MiB of 
+	# alignment padding for the idbloader and u-boot to fit:
+	# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
+	#
+	# U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage
+	PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
+		$@ \
+		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
+		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+		32768
+
+	# Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000
+	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-idbloader.img of="$@" seek=64 conv=notrunc
+	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
+endef
+
+### Devices ###
+define Device/Default
+  PROFILES := Default
+  KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  IMAGES := sysupgrade.img.gz
+  DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
+endef
+
+include $(SUBTARGET).mk
+
+$(eval $(call BuildImage))

image/armv8.mk

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2020 Tobias Maedel
+
+# FIT will be loaded at 0x02080000. Leave 16M for that, align it to 2M and load the kernel after it.
+KERNEL_LOADADDR := 0x03200000
+
+define Device/friendlyarm_nanopi-r5s
+  DEVICE_VENDOR := FriendlyARM
+  DEVICE_MODEL := NanoPi R5S
+  SOC := rk3568
+  UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
+  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
+  DEVICE_PACKAGES := kmod-r8125 kmod-nvme
+endef
+TARGET_DEVICES += friendlyarm_nanopi-r5s

image/mmc.bootscript

@@ -0,0 +1,7 @@
+part uuid mmc ${devnum}:2 uuid
+
+setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait mitigations=off"
+
+load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
+
+bootm ${kernel_addr_r}

image/nanopi-r5s.bootscript

@@ -0,0 +1,7 @@
+part uuid mmc ${devnum}:2 uuid
+
+setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait mitigations=off pcie_aspm=off"
+
+load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
+
+bootm ${kernel_addr_r}

modules.mk

@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2020 OpenWrt.org
+
+define KernelPackage/drm-rockchip
+  SUBMENU:=$(VIDEO_MENU)
+  TITLE:=Rockchip DRM support
+  DEPENDS:=@TARGET_rockchip +kmod-backlight +kmod-drm-kms-helper +kmod-multimedia-input
+  KCONFIG:= \
+	CONFIG_DRM_ROCKCHIP \
+	CONFIG_DRM_LOAD_EDID_FIRMWARE=y \
+	CONFIG_DRM_FBDEV_EMULATION=y \
+	CONFIG_DRM_FBDEV_OVERALLOC=100 \
+	CONFIG_DRM_BRIDGE=y \
+	CONFIG_HDMI=y \
+	CONFIG_PHY_ROCKCHIP_INNO_HDMI \
+	CONFIG_DRM_DW_HDMI \
+	CONFIG_DRM_DW_HDMI_CEC \
+	CONFIG_ROCKCHIP_VOP=y \
+	CONFIG_ROCKCHIP_VOP2=y \
+	CONFIG_ROCKCHIP_ANALOGIX_DP=n \
+	CONFIG_ROCKCHIP_CDN_DP=n \
+	CONFIG_ROCKCHIP_DW_HDMI=y \
+	CONFIG_ROCKCHIP_INNO_HDMI=y \
+	CONFIG_ROCKCHIP_DW_MIPI_DSI=y \
+	CONFIG_ROCKCHIP_LVDS=y \
+	CONFIG_ROCKCHIP_RGB=n \
+	CONFIG_ROCKCHIP_RK3066_HDMI=n \
+	CONFIG_DRM_DP_AUX_BUS \
+	CONFIG_DRM_DW_HDMI_GP_AUDIO=n \
+	CONFIG_DRM_PANEL=y \
+	CONFIG_DRM_PANEL_BRIDGE=y \
+	CONFIG_DRM_PANEL_SIMPLE \
+	CONFIG_MEDIA_CEC_RC=y
+  FILES:= \
+	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \
+	$(LINUX_DIR)/drivers/media/cec/core/cec.ko \
+	$(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/display/drm_dp_aux_bus.ko@le5.15 \
+	$(LINUX_DIR)/drivers/gpu/drm/drm_dma_helper.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/display/drm_display_helper.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
+	$(LINUX_DIR)/drivers/gpu/drm/rockchip/rockchipdrm.ko
+  AUTOLOAD:=$(call AutoProbe,rockchipdrm phy-rockchip-inno-hdmi dw-hdmi-cec)
+endef
+
+define KernelPackage/drm-rockchip/description
+  Direct Rendering Manager (DRM) support for Rockchip
+endef
+
+$(eval $(call KernelPackage,drm-rockchip))
+
+define KernelPackage/saradc-rockchip
+  SUBMENU:=$(IIO_MENU)
+  TITLE:=Rockchip SARADC support
+  DEPENDS:=@TARGET_rockchip +kmod-industrialio-triggered-buffer
+  KCONFIG:= \
+	CONFIG_RESET_CONTROLLER=y \
+	CONFIG_ROCKCHIP_SARADC \
+	CONFIG_IIO_SCMI=n
+  FILES:= \
+	$(LINUX_DIR)/drivers/iio/adc/rockchip_saradc.ko
+  AUTOLOAD:=$(call AutoProbe,rockchip_saradc)
+endef
+
+define KernelPackage/saradc-rockchip/description
+  Support for the SARADC found in SoCs from Rockchip
+endef
+
+$(eval $(call KernelPackage,saradc-rockchip))

patches-6.1/001-gpio-sysfs-build.patch

@@ -0,0 +1,13 @@
+diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
+index 0642f5791..830bc9a8e 100644
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -59,7 +59,7 @@ config DEBUG_GPIO
+ 	  that are most common when setting up new platforms or boards.
+ 
+ config GPIO_SYSFS
+-	bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
++	bool "/sys/class/gpio/... (sysfs interface)"
+ 	depends on SYSFS
+ 	select GPIO_CDEV # We need to encourage the new ABI
+ 	help

patches-6.1/002-add-hwrng-for-rk3568.patch

@@ -0,0 +1,398 @@
+From 7592a44966f7c135d4460b564fcd8d39fe323b68 Mon Sep 17 00:00:00 2001
+From: sbwml <984419930@qq.com>
+Date: Sat, 31 Dec 2022 18:42:34 +0800
+Subject: [PATCH] add hwrng for rk3568
+
+---
+ .../bindings/rng/rockchip,rk3568-rng.yaml     |  60 +++++
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  10 +
+ drivers/char/hw_random/Kconfig                |  14 +
+ drivers/char/hw_random/Makefile               |   1 +
+ drivers/char/hw_random/rk3568-rng.c           | 250 ++++++++++++++++++
+ 5 files changed, 335 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+ create mode 100644 drivers/char/hw_random/rk3568-rng.c
+
+diff --git a/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+new file mode 100644
+index 000000000..c2f5ef69c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip TRNG
++
++description: True Random Number Generator for some Rockchip SoCs
++
++maintainers:
++  - Aurelien Jarno <aurelien@aurel32.net>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3568-rng
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: TRNG clock
++      - description: TRNG AHB clock
++
++  clock-names:
++    items:
++      - const: trng_clk
++      - const: trng_hclk
++
++  resets:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - resets
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3568-cru.h>
++    bus {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      rng@fe388000 {
++        compatible = "rockchip,rk3568-rng";
++        reg = <0x0 0xfe388000 0x0 0x4000>;
++        clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++        clock-names = "trng_clk", "trng_hclk";
++        resets = <&cru SRST_TRNG_NS>;
++      };
++    };
++
++...
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 164708f1e..718171234 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1770,6 +1770,16 @@ usb2phy1_otg: otg-port {
+ 		};
+ 	};
+ 
++	rng: rng@fe388000 {
++		compatible = "rockchip,rk3568-rng";
++		reg = <0x0 0xfe388000 0x0 0x4000>;
++		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++		clock-names = "trng_clk", "trng_hclk";
++		resets = <&cru SRST_TRNG_NS>;
++		reset-names = "reset";
++		status = "disabled";
++	};
++
+ 	pinctrl: pinctrl {
+ 		compatible = "rockchip,rk3568-pinctrl";
+ 		rockchip,grf = <&grf>;
+diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
+index 3da8e85f8..3e20e4421 100644
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -372,6 +372,20 @@ config HW_RANDOM_STM32
+ 
+ 	  If unsure, say N.
+ 
++config HW_RANDOM_ROCKCHIP_RK3568
++	tristate "Rockchip RK3568 True Random Number Generator"
++	depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
++	depends on HAS_IOMEM
++	default HW_RANDOM
++	help
++	  This driver provides kernel-side support for the True Random Number
++	  Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called rockchip-rng.
++
++	  If unsure, say Y.
++
+ config HW_RANDOM_PIC32
+ 	tristate "Microchip PIC32 Random Number Generator support"
+ 	depends on HW_RANDOM && MACH_PIC32
+diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
+index 3e948cf04..460191bcf 100644
+--- a/drivers/char/hw_random/Makefile
++++ b/drivers/char/hw_random/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
+ obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
+ obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
+ obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
++obj-$(CONFIG_HW_RANDOM_ROCKCHIP_RK3568) += rk3568-rng.o
+ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
+ obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
+ obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
+diff --git a/drivers/char/hw_random/rk3568-rng.c b/drivers/char/hw_random/rk3568-rng.c
+new file mode 100644
+index 000000000..b04346b23
+--- /dev/null
++++ b/drivers/char/hw_random/rk3568-rng.c
+@@ -0,0 +1,250 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
++ *
++ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022, Aurelien Jarno
++ * Authors:
++ *  Lin Jinhan <troy.lin@rock-chips.com>
++ *  Aurelien Jarno <aurelien@aurel32.net>
++ */
++#include <linux/clk.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++
++#define RK_RNG_AUTOSUSPEND_DELAY	100
++#define RK_RNG_MAX_BYTE			32
++#define RK_RNG_POLL_PERIOD_US		100
++#define RK_RNG_POLL_TIMEOUT_US		10000
++
++/*
++ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
++ * a tradeoff between speed and quality and has been adjusted to get a quality
++ * of ~900 (~90% of FIPS 140-2 successes).
++ */
++#define RK_RNG_SAMPLE_CNT		1000
++
++/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
++#define TRNG_RST_CTL			0x0004
++#define TRNG_RNG_CTL			0x0400
++#define TRNG_RNG_CTL_LEN_64_BIT		(0x00 << 4)
++#define TRNG_RNG_CTL_LEN_128_BIT	(0x01 << 4)
++#define TRNG_RNG_CTL_LEN_192_BIT	(0x02 << 4)
++#define TRNG_RNG_CTL_LEN_256_BIT	(0x03 << 4)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_0	(0x00 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_1	(0x01 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_2	(0x02 << 2)
++#define TRNG_RNG_CTL_OSC_RING_SPEED_3	(0x03 << 2)
++#define TRNG_RNG_CTL_ENABLE		BIT(1)
++#define TRNG_RNG_CTL_START		BIT(0)
++#define TRNG_RNG_SAMPLE_CNT		0x0404
++#define TRNG_RNG_DOUT_0			0x0410
++#define TRNG_RNG_DOUT_1			0x0414
++#define TRNG_RNG_DOUT_2			0x0418
++#define TRNG_RNG_DOUT_3			0x041c
++#define TRNG_RNG_DOUT_4			0x0420
++#define TRNG_RNG_DOUT_5			0x0424
++#define TRNG_RNG_DOUT_6			0x0428
++#define TRNG_RNG_DOUT_7			0x042c
++
++struct rk_rng {
++	struct hwrng rng;
++	void __iomem *base;
++	struct reset_control *rst;
++	int clk_num;
++	struct clk_bulk_data *clk_bulks;
++};
++
++/* The mask determine the bits that are updated */
++static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
++{
++	writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
++}
++
++static int rk_rng_init(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++	int ret;
++
++	/* start clocks */
++	ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
++	if (ret < 0) {
++		dev_err((struct device *) rk_rng->rng.priv,
++			"Failed to enable clks %d\n", ret);
++		return ret;
++	}
++
++	/* set the sample period */
++	writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
++
++	/* set osc ring speed and enable it */
++	reg = TRNG_RNG_CTL_LEN_256_BIT |
++		   TRNG_RNG_CTL_OSC_RING_SPEED_0 |
++		   TRNG_RNG_CTL_ENABLE;
++	rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++	return 0;
++}
++
++static void rk_rng_cleanup(struct hwrng *rng)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++
++	/* stop TRNG */
++	reg = 0;
++	rk_rng_write_ctl(rk_rng, reg, 0xffff);
++
++	/* stop clocks */
++	clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++	struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++	u32 reg;
++	int ret = 0;
++	int i;
++
++	pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
++
++	/* Start collecting random data */
++	reg = TRNG_RNG_CTL_START;
++	rk_rng_write_ctl(rk_rng, reg, reg);
++
++	ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
++				 !(reg & TRNG_RNG_CTL_START),
++				 RK_RNG_POLL_PERIOD_US,
++				 RK_RNG_POLL_TIMEOUT_US);
++	if (ret < 0)
++		goto out;
++
++	/* Read random data stored in the registers */
++	ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
++	for (i = 0; i < ret; i += 4) {
++		*(u32 *)(buf + i) = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
++	}
++
++out:
++	pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
++	pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
++
++	return ret;
++}
++
++static int rk_rng_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rk_rng *rk_rng;
++	int ret;
++
++	rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
++	if (!rk_rng)
++		return -ENOMEM;
++
++	rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(rk_rng->base))
++		return PTR_ERR(rk_rng->base);
++
++	rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
++	if (rk_rng->clk_num < 0)
++		return dev_err_probe(dev, rk_rng->clk_num,
++				     "Failed to get clks property\n");
++
++	rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
++	if (IS_ERR(rk_rng->rst))
++		return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
++				     "Failed to get reset property\n");
++
++	reset_control_assert(rk_rng->rst);
++	udelay(2);
++	reset_control_deassert(rk_rng->rst);
++
++	platform_set_drvdata(pdev, rk_rng);
++
++	rk_rng->rng.name = dev_driver_string(dev);
++#ifndef CONFIG_PM
++	rk_rng->rng.init = rk_rng_init;
++	rk_rng->rng.cleanup = rk_rng_cleanup;
++#endif
++	rk_rng->rng.read = rk_rng_read;
++	rk_rng->rng.priv = (unsigned long) dev;
++	rk_rng->rng.quality = 900;
++
++	pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
++	pm_runtime_use_autosuspend(dev);
++	pm_runtime_enable(dev);
++
++	ret = devm_hwrng_register(dev, &rk_rng->rng);
++	if (ret)
++		return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
++
++	dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
++
++	return 0;
++}
++
++static int rk_rng_remove(struct platform_device *pdev)
++{
++	pm_runtime_disable(&pdev->dev);
++
++	return 0;
++}
++
++#ifdef CONFIG_PM
++static int rk_rng_runtime_suspend(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	rk_rng_cleanup(&rk_rng->rng);
++
++	return 0;
++}
++
++static int rk_rng_runtime_resume(struct device *dev)
++{
++	struct rk_rng *rk_rng = dev_get_drvdata(dev);
++
++	return rk_rng_init(&rk_rng->rng);
++}
++#endif
++
++static const struct dev_pm_ops rk_rng_pm_ops = {
++	SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
++				rk_rng_runtime_resume, NULL)
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
++};
++
++static const struct of_device_id rk_rng_dt_match[] = {
++	{
++		.compatible = "rockchip,rk3568-rng",
++	},
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
++
++static struct platform_driver rk_rng_driver = {
++	.driver	= {
++		.name	= "rk3568-rng",
++		.pm	= &rk_rng_pm_ops,
++		.of_match_table = rk_rng_dt_match,
++	},
++	.probe	= rk_rng_probe,
++	.remove = rk_rng_remove,
++};
++
++module_platform_driver(rk_rng_driver);
++
++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
++MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.34.1
+

patches-6.1/003-rk3568-general-patch-set.patch

@@ -0,0 +1,439 @@
+diff -Naur a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
+--- a/drivers/clk/rockchip/clk-half-divider.c	2022-07-31 17:03:01.000000000 -0400
++++ b/drivers/clk/rockchip/clk-half-divider.c	2022-08-09 17:00:56.992472371 -0400
+@@ -166,7 +166,7 @@
+ 					  unsigned long flags,
+ 					  spinlock_t *lock)
+ {
+-	struct clk_hw *hw = ERR_PTR(-ENOMEM);
++	struct clk_hw *hw;
+ 	struct clk_mux *mux = NULL;
+ 	struct clk_gate *gate = NULL;
+ 	struct clk_divider *div = NULL;
+diff -Naur a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
+--- a/drivers/usb/dwc3/dwc3-of-simple.c	2022-07-31 17:03:01.000000000 -0400
++++ b/drivers/usb/dwc3/dwc3-of-simple.c	2022-08-09 17:00:56.994472344 -0400
+@@ -30,12 +30,16 @@
+ 	bool			need_reset;
+ };
+ 
++struct dwc3_of_simple_data {
++	bool			need_reset;
++};
++
+ static int dwc3_of_simple_probe(struct platform_device *pdev)
+ {
+ 	struct dwc3_of_simple	*simple;
+ 	struct device		*dev = &pdev->dev;
+ 	struct device_node	*np = dev->of_node;
+-
++	const struct dwc3_of_simple_data *data = of_device_get_match_data(dev);
+ 	int			ret;
+ 
+ 	simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
+@@ -49,8 +53,8 @@
+ 	 * Some controllers need to toggle the usb3-otg reset before trying to
+ 	 * initialize the PHY, otherwise the PHY times out.
+ 	 */
+-	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
+-		simple->need_reset = true;
++	if (data->need_reset)
++		simple->need_reset = data->need_reset;
+ 
+ 	simple->resets = of_reset_control_array_get(np, false, true,
+ 						    true);
+@@ -170,13 +174,34 @@
+ 			dwc3_of_simple_runtime_resume, NULL)
+ };
+ 
++static const struct dwc3_of_simple_data dwc3_of_simple_data_rk3399 = {
++	.need_reset = true,
++};
++
+ static const struct of_device_id of_dwc3_simple_match[] = {
+-	{ .compatible = "rockchip,rk3399-dwc3" },
+-	{ .compatible = "cavium,octeon-7130-usb-uctl" },
+-	{ .compatible = "sprd,sc9860-dwc3" },
+-	{ .compatible = "allwinner,sun50i-h6-dwc3" },
+-	{ .compatible = "hisilicon,hi3670-dwc3" },
+-	{ .compatible = "intel,keembay-dwc3" },
++	{
++		.compatible = "allwinner,sun50i-h6-dwc3",
++	},
++	{
++		.compatible = "cavium,octeon-7130-usb-uctl",
++	},
++	{
++		.compatible = "hisilicon,hi3670-dwc3",
++	},
++	{
++		.compatible = "intel,keembay-dwc3",
++	},
++	{
++		.compatible = "rockchip,rk3399-dwc3",
++		.data = &dwc3_of_simple_data_rk3399,
++	},
++	{
++		.compatible = "rockchip,rk3568-dwc3",
++		.data = &dwc3_of_simple_data_rk3399,
++	},
++	{
++		.compatible = "sprd,sc9860-dwc3",
++	},
+ 	{ /* Sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
+diff -Naur a/kernel/dma/pool.c b/kernel/dma/pool.c
+--- a/kernel/dma/pool.c	2022-07-31 17:03:01.000000000 -0400
++++ b/kernel/dma/pool.c	2022-08-09 17:00:56.992472371 -0400
+@@ -189,13 +189,10 @@
+ 	int ret = 0;
+ 
+ 	/*
+-	 * If coherent_pool was not used on the command line, default the pool
+-	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1.
++	 * Use 2MiB as default pool size.
+ 	 */
+ 	if (!atomic_pool_size) {
+-		unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
+-		pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
+-		atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
++		atomic_pool_size = SZ_2M;
+ 	}
+ 	INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
+ 
+diff -Naur a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
+--- a/sound/soc/codecs/rt5651.c	2022-07-31 17:03:01.000000000 -0400
++++ b/sound/soc/codecs/rt5651.c	2022-08-09 17:00:56.993472358 -0400
+@@ -24,6 +24,7 @@
+ #include <sound/initval.h>
+ #include <sound/tlv.h>
+ #include <sound/jack.h>
++#include <linux/clk.h>
+ 
+ #include "rl6231.h"
+ #include "rt5651.h"
+@@ -1511,6 +1512,7 @@
+ static int rt5651_set_bias_level(struct snd_soc_component *component,
+ 			enum snd_soc_bias_level level)
+ {
++	struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
+ 	switch (level) {
+ 	case SND_SOC_BIAS_PREPARE:
+ 		if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
+@@ -1518,6 +1520,13 @@
+ 				snd_soc_component_update_bits(component, RT5651_D_MISC,
+ 						    0xc00, 0xc00);
+ 		}
++		if (!IS_ERR(rt5651->mclk)){
++			if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
++				clk_disable_unprepare(rt5651->mclk);
++			} else {
++				clk_prepare_enable(rt5651->mclk);
++			}
++		}
+ 		break;
+ 	case SND_SOC_BIAS_STANDBY:
+ 		if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
+@@ -2059,6 +2068,13 @@
+ {
+ 	struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
+ 
++	/* Check if MCLK provided */
++	rt5651->mclk = devm_clk_get(component->dev, "mclk");
++	if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
++		dev_err(component->dev, "unable to get mclk\n");
++		return -EPROBE_DEFER;
++	}
++
+ 	rt5651->component = component;
+ 
+ 	snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
+diff -Naur a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
+--- a/sound/soc/codecs/rt5651.h	2022-07-31 17:03:01.000000000 -0400
++++ b/sound/soc/codecs/rt5651.h	2022-08-09 17:00:56.994472344 -0400
+@@ -2097,6 +2097,7 @@
+ 
+ 	int dmic_en;
+ 	bool hp_mute;
++	struct clk *mclk;
+ };
+ 
+ #endif /* __RT5651_H__ */
+diff -Naur a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2022-07-10 17:40:51.000000000 -0400
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2022-07-11 05:18:34.000000000 -0400
+@@ -91,80 +91,88 @@
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
+-		},
+-	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
+-		},
+-	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
+-		},
+-	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
+-		},
+-	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
++		},
++	},  {
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
++		},
++	},  {
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
++		},
++	},  {
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
++		},
++	},  {
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
++		},
++	},  {
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
++		},
++	},  {
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
++		340000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++		},
++	},  {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+-	}, {
++	},  {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };
+@@ -172,20 +180,8 @@
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
++		600000000, { 0x0000, 0x0000, 0x0000 },
++	},  {
+ 		~0UL,      { 0x0000, 0x0000, 0x0000},
+ 	}
+ };
+@@ -195,6 +191,7 @@
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+ 	{ 148500000, 0x802b, 0x0004, 0x028d},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
++	{ 594000000, 0x8039, 0x0000, 0x019d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
+@@ -240,26 +237,6 @@
+ 	return 0;
+ }
+ 
+-static enum drm_mode_status
+-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
+-			    const struct drm_display_info *info,
+-			    const struct drm_display_mode *mode)
+-{
+-	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+-	int pclk = mode->clock * 1000;
+-	bool valid = false;
+-	int i;
+-
+-	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		if (pclk == mpll_cfg[i].mpixelclock) {
+-			valid = true;
+-			break;
+-		}
+-	}
+-
+-	return (valid) ? MODE_OK : MODE_BAD;
+-}
+-
+ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
+ {
+ }
+@@ -425,7 +402,6 @@
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg = rockchip_mpll_cfg,
+ 	.cur_ctr = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -442,7 +418,6 @@
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -462,7 +437,6 @@
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg = rockchip_mpll_cfg,
+ 	.cur_ctr = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -480,7 +454,6 @@
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -493,7 +466,6 @@
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -597,6 +569,14 @@
+ 	}
+ 
+ 	if (hdmi->chip_data == &rk3568_chip_data) {
++		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
++			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK,
++					   RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK));
++	}
++
++	if (hdmi->chip_data == &rk3568_chip_data) {
+ 		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
+ 			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
+ 					   RK3568_HDMI_SCLIN_MSK,

patches-6.1/004-arm64-add-dts-rk3568-nanopi-r5s.patch

@@ -0,0 +1,10 @@
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index ef79a6728..16b0bd2fb 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -65,4 +65,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb

patches-6.1/005-friendlyelec-nanopi-series.patch

@@ -0,0 +1,212 @@
+From e134dcd7dda9048f4ac2cab96322a8a7f08a9d22 Mon Sep 17 00:00:00 2001
+From: sbwml <984419930@qq.com>
+Date: Sat, 12 Nov 2022 10:24:30 +0800
+Subject: [PATCH] friendlyelec-nanopi-series
+
+---
+ drivers/soc/Kconfig               |   1 +
+ drivers/soc/Makefile              |   1 +
+ drivers/soc/friendlyelec/Kconfig  |  11 +++
+ drivers/soc/friendlyelec/Makefile |   1 +
+ drivers/soc/friendlyelec/board.c  | 143 ++++++++++++++++++++++++++++++
+ 5 files changed, 157 insertions(+)
+ create mode 100644 drivers/soc/friendlyelec/Kconfig
+ create mode 100644 drivers/soc/friendlyelec/Makefile
+ create mode 100644 drivers/soc/friendlyelec/board.c
+
+diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
+index e461c0711..a65fa9f4f 100644
+--- a/drivers/soc/Kconfig
++++ b/drivers/soc/Kconfig
+@@ -27,5 +27,6 @@ source "drivers/soc/ti/Kconfig"
+ source "drivers/soc/ux500/Kconfig"
+ source "drivers/soc/versatile/Kconfig"
+ source "drivers/soc/xilinx/Kconfig"
++source "drivers/soc/friendlyelec/Kconfig"
+ 
+ endmenu
+diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
+index 69ba6508c..16ac16900 100644
+--- a/drivers/soc/Makefile
++++ b/drivers/soc/Makefile
+@@ -33,3 +33,4 @@ obj-y				+= ti/
+ obj-$(CONFIG_ARCH_U8500)	+= ux500/
+ obj-$(CONFIG_PLAT_VERSATILE)	+= versatile/
+ obj-y				+= xilinx/
++obj-$(CONFIG_VENDOR_FRIENDLYELEC)	+= friendlyelec/
+diff --git a/drivers/soc/friendlyelec/Kconfig b/drivers/soc/friendlyelec/Kconfig
+new file mode 100644
+index 000000000..642629ab7
+--- /dev/null
++++ b/drivers/soc/friendlyelec/Kconfig
+@@ -0,0 +1,11 @@
++#
++# Machine drivers
++#
++
++if ARCH_ROCKCHIP
++
++config VENDOR_FRIENDLYELEC
++	bool "FriendlyElec board based on Rockchip SoCs"
++	default n
++
++endif
+diff --git a/drivers/soc/friendlyelec/Makefile b/drivers/soc/friendlyelec/Makefile
+new file mode 100644
+index 000000000..870542f05
+--- /dev/null
++++ b/drivers/soc/friendlyelec/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_VENDOR_FRIENDLYELEC)	+= board.o
+diff --git a/drivers/soc/friendlyelec/board.c b/drivers/soc/friendlyelec/board.c
+new file mode 100644
+index 000000000..886a8e1f7
+--- /dev/null
++++ b/drivers/soc/friendlyelec/board.c
+@@ -0,0 +1,143 @@
++/*
++ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, you can access it online at
++ * http://www.gnu.org/licenses/gpl-2.0.html.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/crc32.h>
++#include <linux/nvmem-consumer.h>
++
++#define BOARD_MANF "FriendlyELEC Computer Tech. Co., Ltd."
++
++static const char *board_mach;
++static const char *board_name;
++static u32 board_rev;
++static u32 board_serial_high, board_serial_low;
++
++static ssize_t board_sys_info_show(struct device *dev,
++		struct device_attribute *attr,
++		char *buf)
++{
++	char *s = buf;
++
++	s += sprintf(s, "Hardware\t: %s\n", board_mach);
++	s += sprintf(s, "Revision\t: %04x\n", board_rev);
++	s += sprintf(s, "Serial\t\t: %08x%08x\n",
++			board_serial_high, board_serial_low);
++	s += sprintf(s, "\nModel\t\t: %s\n", board_name);
++	s += sprintf(s, "Manufacturer\t: %s\n", BOARD_MANF);
++
++	return (s - buf);
++}
++
++static struct device_attribute board_attr_info =
++	__ATTR(info, S_IRUGO, board_sys_info_show, NULL);
++
++static int rockchip_cpuinfo_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct nvmem_cell *cell;
++	unsigned char *efuse_buf, buf[16];
++	size_t len;
++	int i;
++
++	cell = nvmem_cell_get(dev, "id");
++	if (IS_ERR(cell)) {
++		dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
++		return PTR_ERR(cell);
++	}
++
++	efuse_buf = nvmem_cell_read(cell, &len);
++	nvmem_cell_put(cell);
++
++	if (len != 16) {
++		kfree(efuse_buf);
++		dev_err(dev, "invalid id len: %zu\n", len);
++		return -EINVAL;
++	}
++
++	for (i = 0; i < 8; i++) {
++		buf[i] = efuse_buf[1 + (i << 1)];
++		buf[i + 8] = efuse_buf[i << 1];
++	}
++
++	kfree(efuse_buf);
++
++	board_serial_low = crc32(0, buf, 8);
++	board_serial_high = crc32(board_serial_low, buf + 8, 8);
++
++	dev_info(dev, "Serial\t\t: %08x%08x\n",
++		 board_serial_high, board_serial_low);
++
++	return 0;
++}
++
++static int board_sys_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device_node *root;
++
++	root = of_find_node_by_path("/");
++
++	of_property_read_u32(np, "hwrev", &board_rev);
++
++	if (of_property_read_string(np, "machine", &board_mach))
++		of_property_read_string(root, "compatible", &board_mach);
++
++	if (of_property_read_string(np, "model", &board_name))
++		of_property_read_string(root, "model", &board_name);
++
++	of_node_put(root);
++
++	rockchip_cpuinfo_probe(pdev);
++
++	device_create_file(&pdev->dev, &board_attr_info);
++
++	return 0;
++}
++
++static const struct of_device_id board_sys_of_match[] = {
++	{ .compatible = "friendlyelec,board" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, board_sys_of_match);
++
++static struct platform_driver board_sys_driver = {
++	.probe = board_sys_probe,
++	.driver = {
++		.name = "friendlyelec-board",
++		.of_match_table = board_sys_of_match,
++	},
++};
++
++static int __init board_sys_init(void)
++{
++	return platform_driver_register(&board_sys_driver);
++}
++late_initcall(board_sys_init);
++
++MODULE_AUTHOR("support@friendlyarm.com");
++MODULE_DESCRIPTION("FriendlyElec NanoPi Series Machine Driver");
++MODULE_LICENSE("GPL v2");
+-- 
+2.34.1
+

patches-6.1/006-rk356x-1992-MHz.patch

@@ -0,0 +1,14 @@
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -127,6 +127,11 @@
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1050000 1050000 1150000>;
+ 		};
++
++		opp-1992000000 {
++			opp-hz = /bits/ 64 <1992000000>;
++			opp-microvolt = <1150000 1150000 1150000>;
++		};
+ 	};
+ 
+ 	display_subsystem: display-subsystem {

patches-6.1/007-rockchip-p3phy-fw.patch

@@ -0,0 +1,92 @@
+From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Mon, 11 Jul 2022 20:35:52 +0800
+Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
+
+This fw fix some RX issue:
+1. connect detect error;
+2. transfer error in ssd huge data write(more than 10GB).
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
+---
+ drivers/phy/phy-rockchip-snps-pcie3.c  |   36 +-
+ drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
+ 2 files changed, 8225 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -20,6 +20,7 @@
+ 
+ /* Register for RK3568 */
+ #define GRF_PCIE30PHY_CON1			0x4
++#define GRF_PCIE30PHY_CON4			0x10
+ #define GRF_PCIE30PHY_CON6			0x18
+ #define GRF_PCIE30PHY_CON9			0x24
+ #define GRF_PCIE30PHY_DA_OCM			(BIT(15) | BIT(31))
+@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops {
+ 	int (*phy_init)(struct rockchip_p3phy_priv *priv);
+ };
+ 
++static u16 phy_fw[] = {
++	#include "p3phy.fw"
++};
++
+ static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+ {
+ 	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+@@ -87,13 +92,14 @@ static int rockchip_p3phy_rk3568_init(st
+ {
+ 	struct phy *phy = priv->phy;
+ 	bool bifurcation = false;
++	int i;
+ 	int ret;
+ 	u32 reg;
+ 
+ 	/* Deassert PCIe PMA output clamp mode */
+ 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
+ 
+-	for (int i = 0; i < priv->num_lanes; i++) {
++	for (i = 0; i < priv->num_lanes; i++) {
+ 		dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
+ 		if (priv->lanes[i] > 1)
+ 			bifurcation = true;
+@@ -112,16 +118,35 @@ static int rockchip_p3phy_rk3568_init(st
+ 			     GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
+ 	}
+ 
++	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
++		     (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
++	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
++		     (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
++
+ 	reset_control_deassert(priv->p30phy);
+ 
+ 	ret = regmap_read_poll_timeout(priv->phy_grf,
+ 				       GRF_PCIE30PHY_STATUS0,
+ 				       reg, SRAM_INIT_DONE(reg),
+ 				       0, 500);
+-	if (ret)
++	if (ret) {
+ 		dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
+ 		       __func__, reg);
+-	return ret;
++		return ret;
++	}
++
++	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
++		     (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
++	for (i = 0; i < 8192; i++)
++		writel(phy_fw[i], priv->mmio + (i<<2));
++
++	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
++		     (0x0 << 8) | (0x3 << (8 + 16)));
++	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
++		     (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
++
++	dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
++	return 0;
+ }
+ 
+ static const struct rockchip_p3phy_ops rk3568_ops = {

patches-6.1/109-arm64-dts-rockchip-rk356x-Fix-PCIe-register-map.patch

@@ -0,0 +1,40 @@
+From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
+From: Andrew Powers-Holmes <aholmes@omnom.net>
+Date: Sat, 12 Nov 2022 22:41:26 +1100
+Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
+ range mappings
+
+The register and range mappings for the PCIe controller in Rockchip's
+RK356x SoCs are incorrect. Replace them with corrected values from the
+vendor BSP sources, updated to match current DT schema.
+
+Tested-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi |  7 ++++---
+ 2 files changed, 12 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -951,7 +951,7 @@ pcie2x1: pcie@fe260000 {
+ 		compatible = "rockchip,rk3568-pcie";
+ 		reg = <0x3 0xc0000000 0x0 0x00400000>,
+ 		      <0x0 0xfe260000 0x0 0x00010000>,
+-		      <0x3 0x3f000000 0x0 0x01000000>;
++		      <0x0 0xf4000000 0x0 0x00100000>;
+ 		reg-names = "dbi", "apb", "config";
+ 		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+@@ -980,8 +980,9 @@ pcie2x1: pcie@fe260000 {
+ 		phys = <&combphy2 PHY_TYPE_PCIE>;
+ 		phy-names = "pcie-phy";
+ 		power-domains = <&power RK3568_PD_PIPE>;
+-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
+-			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
++		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
++			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
+ 		resets = <&cru SRST_PCIE20_POWERUP>;
+ 		reset-names = "pipe";
+ 		#address-cells = <3>;

patches-6.1/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch

@@ -0,0 +1,94 @@
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -1133,6 +1133,14 @@ config SOCIONEXT_SYNQUACER_PREITS
+ 
+ 	  If unsure, say Y.
+ 
++config ROCKCHIP_ERRATUM_114514
++	bool "Rockchip RK3568 force no_local_cache"
++	default y
++	help
++	  They consider this as a SoC implement design instead of a bug.
++
++	  If unsure, say Y.
++
+ endmenu # "ARM errata workarounds via the alternatives framework"
+ 
+ choice
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -64,7 +64,7 @@
+ 		compatible = "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		bus-range = <0x0 0xf>;
++		bus-range = <0x10 0x1f>;
+ 		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ 			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ 			 <&cru CLK_PCIE30X1_AUX_NDFT>;
+@@ -87,7 +87,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <3>;
+-		msi-map = <0x0 &gic 0x1000 0x1000>;
++		msi-map = <0x1000 &its 0x1000 0x1000>;
+ 		num-lanes = <1>;
+ 		phys = <&pcie30phy>;
+ 		phy-names = "pcie-phy";
+@@ -116,7 +116,7 @@
+ 		compatible = "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		bus-range = <0x0 0xf>;
++		bus-range = <0x20 0x2f>;
+ 		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ 			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ 			 <&cru CLK_PCIE30X2_AUX_NDFT>;
+@@ -139,7 +139,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <3>;
+-		msi-map = <0x0 &gic 0x2000 0x1000>;
++		msi-map = <0x2000 &its 0x2000 0x1000>;
+ 		num-lanes = <2>;
+ 		phys = <&pcie30phy>;
+ 		phy-names = "pcie-phy";
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -315,14 +315,21 @@
+ 
+ 	gic: interrupt-controller@fd400000 {
+ 		compatible = "arm,gic-v3";
++		#interrupt-cells = <3>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		interrupt-controller;
++
+ 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+-		      <0x0 0xfd460000 0 0x80000>; /* GICR */
++		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
+ 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-controller;
+-		#interrupt-cells = <3>;
+-		mbi-alias = <0x0 0xfd410000>;
+-		mbi-ranges = <296 24>;
+-		msi-controller;
++		its: interrupt-controller@fd440000 {
++			compatible = "arm,gic-v3-its";
++			msi-controller;
++			#msi-cells = <1>;
++			reg = <0x0 0xfd440000 0x0 0x20000>;
++		};
+ 	};
+ 
+ 	usb_host0_ehci: usb@fd800000 {
+@@ -975,7 +982,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <2>;
+-		msi-map = <0x0 &gic 0x0 0x1000>;
++		msi-map = <0x0 &its 0x0 0x1000>;
+ 		num-lanes = <1>;
+ 		phys = <&combphy2 PHY_TYPE_PCIE>;
+ 		phy-names = "pcie-phy";

patches-6.1/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch

@@ -0,0 +1,198 @@
+From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Thu, 3 Jun 2021 11:36:35 -0400
+Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
+
+---
+ drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
+ 1 file changed, 65 insertions(+), 5 deletions(-)
+
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -45,6 +45,7 @@
+ 
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
++#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE	(1 << 2)
+ 
+ #define RD_LOCAL_LPI_ENABLED                    BIT(0)
+ #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
+@@ -2172,6 +2173,11 @@ static struct page *its_allocate_prop_table(gfp_t gfp_flags)
+ {
+ 	struct page *prop_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+ 		return NULL;
+@@ -2295,6 +2301,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+ 	void *base;
++	gfp_t gfp_flags;
+ 
+ 	psz = baser->psz;
+ 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
+@@ -2306,7 +2313,10 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2353,6 +2363,13 @@ retry_baser:
+ 	its_write_baser(its, baser, val);
+ 	tmp = baser->val;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		if (tmp & GITS_BASER_SHAREABILITY_MASK)
++			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++		else
++			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
++	}
++
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+ 		 * Shareability didn't stick. Just use
+@@ -2935,6 +2952,10 @@ static struct page *its_allocate_pending_table(gfp_t gfp_flags)
+ {
+ 	struct page *pend_page;
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		gfp_flags |= GFP_DMA;
++	}
++
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3092,6 +3113,9 @@ static void its_cpu_init_lpis(void)
+ 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ 			/*
+@@ -3116,6 +3140,9 @@ static void its_cpu_init_lpis(void)
+ 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -3278,7 +3305,12 @@ static bool its_alloc_table_entry(struct its_node *its,
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
++		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++			gfp_flags |= GFP_DMA;
++		}
++
++		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3367,6 +3399,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 	int nr_lpis;
+ 	int nr_ites;
+ 	int sz;
++	gfp_t gfp_flags;
+ 
+ 	if (!its_alloc_device_table(its, dev_id))
+ 		return NULL;
+@@ -3374,7 +3407,11 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 	if (WARN_ON(!is_power_of_2(nvecs)))
+ 		nvecs = roundup_pow_of_two(nvecs);
+ 
+-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++	gfp_flags = GFP_KERNEL;
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		gfp_flags |= GFP_DMA;
++
++	dev = kzalloc(sizeof(*dev), gfp_flags);
+ 	/*
+ 	 * Even if the device wants a single LPI, the ITT must be
+ 	 * sized as a power of two (and you need at least one bit...).
+@@ -3382,7 +3419,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -4705,6 +4742,13 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
+ 	return true;
+ }
+ 
++static bool __maybe_unused its_enable_quirk_rk3568(void *data)
++{
++	gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
++
++	return true;
++}
++
+ static const struct gic_quirk its_quirks[] = {
+ #ifdef CONFIG_CAVIUM_ERRATUM_22375
+ 	{
+@@ -4750,6 +4794,14 @@ static const struct gic_quirk its_quirks[] = {
+ 		.mask	= 0xffffffff,
+ 		.init	= its_enable_quirk_hip07_161600802,
+ 	},
++#endif
++#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
++	{
++		.desc	= "ITS: Rockchip erratum 114514",
++		.iidr	= 0x0201743b,
++		.mask	= 0xffffffff,
++		.init	= its_enable_quirk_rk3568,
++	},
+ #endif
+ 	{
+ 	}
+@@ -4974,6 +5026,7 @@ static int __init its_probe_one(struct resource *res,
+ 	struct page *page;
+ 	u32 ctlr;
+ 	int err;
++	gfp_t gfp_flags;
+ 
+ 	its_base = its_map_one(res, &err);
+ 	if (!its_base)
+@@ -5042,7 +5095,9 @@ static int __init its_probe_one(struct resource *res,
+ 
+ 	its->numa_node = numa_node;
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
++
++	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
+@@ -5073,6 +5128,9 @@ static int __init its_probe_one(struct resource *res,
+ 	gits_write_cbaser(baser, its->base + GITS_CBASER);
+ 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ 			/*

patches-6.1/990-arm64-build-boot-image.patch

@@ -0,0 +1,25 @@
+--- a/arch/arm64/Makefile
++++ b/arch/arm64/Makefile
+@@ -158,8 +158,12 @@ endif
+ all:	$(notdir $(KBUILD_IMAGE))
+ 
+ 
++DTBS := rk35*-nanopi*.dtb
+ Image vmlinuz.efi: vmlinux
+ 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
++	$(Q)scripts/mkkrnlimg $(objtree)/arch/arm64/boot/Image $(objtree)/kernel.img >/dev/null
++	@echo '  Image:  kernel.img is ready'
++	$(Q)$(srctree)/scripts/mkimg --dtb $(DTBS)
+ 
+ Image.%: Image
+ 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+--- a/scripts/Makefile
++++ b/scripts/Makefile
+@@ -10,6 +10,7 @@ hostprogs-always-$(CONFIG_BUILDTIME_TABLE_SORT)		+= sorttable
+ hostprogs-always-$(CONFIG_ASN1)				+= asn1_compiler
+ hostprogs-always-$(CONFIG_MODULE_SIG_FORMAT)		+= sign-file
+ hostprogs-always-$(CONFIG_SYSTEM_EXTRA_CERTIFICATE)	+= insert-sys-cert
++hostprogs-always-$(CONFIG_ARM64)			+= resource_tool mkkrnlimg
+ hostprogs-always-$(CONFIG_RUST)				+= generate_rust_target
+ 
+ generate_rust_target-rust := y

patches-6.1/991-fix-arm64-kvm-for-openwrt.patch

@@ -0,0 +1,12 @@
+--- a/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c
++++ b/arch/arm64/kvm/hyp/nvhe/gen-hyprel.c
+@@ -286,7 +286,9 @@ static void init_elf(const char *path)
+ 	assert_eq(elf.ehdr->e_ident[EI_CLASS], ELFCLASS64, "%u");
+ 	assert_eq(elf.ehdr->e_ident[EI_DATA], ELFENDIAN, "%u");
+ 	assert_eq(elf16toh(elf.ehdr->e_type), ET_REL, "%u");
++#ifdef EM_AARCH64
+ 	assert_eq(elf16toh(elf.ehdr->e_machine), EM_AARCH64, "%u");
++#endif
+ 
+ 	/* Populate fields of the global struct. */
+ 	elf.sh_table = section_by_off(elf64toh(elf.ehdr->e_shoff));