// SPDX-License-Identifier: (GPL-2.0+ OR MIT)


/dts-v1/;
#include "rk3568-nanopi-common.dtsi"

/ {
	model = "FriendlyElec NanoPi R5S";
	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
	};

	fan: pwm-fan {
		compatible = "pwm-fan";
		cooling-levels = <0 18 60 100 255>;
		#cooling-cells = <2>;
		fan-supply = <&vcc5v0_sysp>;
		pwms = <&pwm0 0 50000 0>;
	};

	gpio-leds {
		compatible = "gpio-leds";

		sys_led: led-sys {
			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
			label = "red:power";
			linux,default-trigger = "heartbeat";
			pinctrl-names = "default";
			pinctrl-0 = <&sys_led_pin>;
		};

		wan_led: led-wan {
			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
			label = "green:wan";
			pinctrl-names = "default";
			pinctrl-0 = <&wan_led_pin>;
		};

		lan1_led: led-lan1 {
			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
			label = "green:lan1";
			pinctrl-names = "default";
			pinctrl-0 = <&lan1_led_pin>;
		};

		lan2_led: led-lan2 {
			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
			label = "green:lan2";
			pinctrl-names = "default";
			pinctrl-0 = <&lan2_led_pin>;
		};
	};
};

&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy0>;
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;
	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 15ms, 50ms for rtl8211f */
	snps,reset-delays-us = <0 15000 50000>;
	tx_delay = <0x3c>;
	rx_delay = <0x2f>;
	status = "okay";
};

&mdio0 {
	rgmii_phy0: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		pinctrl-0 = <&eth_phy0_reset_pin>;
		pinctrl-names = "default";
		realtek,led-data = <0x6d60>;
	};
};

&pcie2x1 {
	num-lanes = <1>;
	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pcie@0,0 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;

		rtl8125_1: pcie@1,0 {
			compatible = "pci10ec,8125";
			reg = <0x000000 0 0 0 0>;

			realtek,led-data = <0x0 0x0 0x2b 0x200>;
		};
	};
};

&pcie30phy {
	data-lanes = <1 2>;
	status = "okay";
};

&pcie3x1 {
	num-lanes = <1>;
	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";

	pcie@0,0 {
		reg = <0x00100000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;

		rtl8125_2: pcie@10,0 {
			compatible = "pci10ec,8125";
			reg = <0x000000 0 0 0 0>;

			realtek,led-data = <0x0 0x0 0x2b 0x200>;
		};
	};
};

&pcie3x2 {
	num-lanes = <1>;
	num-ib-windows = <8>;
	num-ob-windows = <8>;
	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie>;
	status = "okay";
};

&pinctrl {
	gmac0 {
		eth_phy0_reset_pin: eth-phy0-reset-pin {
			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	gpio-leds {
		sys_led_pin: sys-led-pin {
			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		wan_led_pin: wan-led-pin {
			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		lan1_led_pin: lan1-led-pin {
			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		lan2_led_pin: lan2-led-pin {
			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	gpio-key {
		key1_pin: key1-pin {
			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&pwm0 {
	status = "okay";
};