96 lines
3.4 KiB
Diff
96 lines
3.4 KiB
Diff
From dd49ee4614cfb0b1f627c4353b60cecfe998a374 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 11 Dec 2023 19:58:05 +0800
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Subject: [PATCH] drm/rockchip: vop2: Set YUV/RGB overlay mode
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Set overlay mode register according to the
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output mode is yuv or rgb.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://patchwork.freedesktop.org/patch/msgid/20231211115805.1785073-1-andyshrk@163.com
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---
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drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 +
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 17 ++++++++++++++---
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 1 +
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3 files changed, 16 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
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@@ -48,6 +48,7 @@ struct rockchip_crtc_state {
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int output_bpc;
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int output_flags;
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bool enable_afbc;
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+ bool yuv_overlay;
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u32 bus_format;
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u32 bus_flags;
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int color_space;
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -1625,6 +1625,8 @@ static void vop2_crtc_atomic_enable(stru
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vop2->enable_count++;
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+ vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
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+
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vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
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polflags = 0;
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@@ -1652,7 +1654,7 @@ static void vop2_crtc_atomic_enable(stru
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if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
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dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
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- if (is_yuv_output(vcstate->bus_format))
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+ if (vcstate->yuv_overlay)
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dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
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vop2_dither_setup(crtc, &dsp_ctrl);
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@@ -1961,10 +1963,12 @@ static void vop2_setup_layer_mixer(struc
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u16 hdisplay;
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u32 bg_dly;
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u32 pre_scan_dly;
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+ u32 ovl_ctrl;
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int i;
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struct vop2_video_port *vp0 = &vop2->vps[0];
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struct vop2_video_port *vp1 = &vop2->vps[1];
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struct vop2_video_port *vp2 = &vop2->vps[2];
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+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
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adjusted_mode = &vp->crtc.state->adjusted_mode;
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hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
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@@ -1977,7 +1981,15 @@ static void vop2_setup_layer_mixer(struc
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pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
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vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
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- vop2_writel(vop2, RK3568_OVL_CTRL, 0);
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+ ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
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+ ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
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+ if (vcstate->yuv_overlay)
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+ ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
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+ else
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+ ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);
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+
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+ vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);
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+
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port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
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port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
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@@ -2051,7 +2063,6 @@ static void vop2_setup_layer_mixer(struc
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vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
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vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
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- vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);
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}
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static void vop2_setup_dly_for_windows(struct vop2 *vop2)
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
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@@ -401,6 +401,7 @@ enum dst_factor_mode {
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#define VOP2_COLOR_KEY_MASK BIT(31)
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#define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
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+#define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp)
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#define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24)
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