424 lines
11 KiB
Diff
424 lines
11 KiB
Diff
--- a/drivers/clk/rockchip/clk-half-divider.c
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+++ b/drivers/clk/rockchip/clk-half-divider.c
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@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdi
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unsigned long flags,
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spinlock_t *lock)
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{
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- struct clk_hw *hw = ERR_PTR(-ENOMEM);
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+ struct clk_hw *hw;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -92,74 +92,70 @@ static struct rockchip_hdmi *to_rockchip
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static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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- 27000000, {
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- { 0x00b3, 0x0000},
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- { 0x2153, 0x0000},
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- { 0x40f3, 0x0000}
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+ 30666000, {
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+ { 0x00b3, 0x0000 },
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+ { 0x2153, 0x0000 },
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+ { 0x40f3, 0x0000 },
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},
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}, {
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- 36000000, {
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- { 0x00b3, 0x0000},
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- { 0x2153, 0x0000},
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- { 0x40f3, 0x0000}
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+ 36800000, {
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+ { 0x00b3, 0x0000 },
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+ { 0x2153, 0x0000 },
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+ { 0x40a2, 0x0001 },
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},
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}, {
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- 40000000, {
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- { 0x00b3, 0x0000},
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- { 0x2153, 0x0000},
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- { 0x40f3, 0x0000}
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+ 46000000, {
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+ { 0x00b3, 0x0000 },
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+ { 0x2142, 0x0001 },
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+ { 0x40a2, 0x0001 },
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},
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}, {
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- 54000000, {
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- { 0x0072, 0x0001},
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- { 0x2142, 0x0001},
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- { 0x40a2, 0x0001},
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+ 61333000, {
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+ { 0x0072, 0x0001 },
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+ { 0x2142, 0x0001 },
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+ { 0x40a2, 0x0001 },
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},
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}, {
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- 65000000, {
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- { 0x0072, 0x0001},
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- { 0x2142, 0x0001},
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- { 0x40a2, 0x0001},
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+ 73600000, {
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+ { 0x0072, 0x0001 },
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+ { 0x2142, 0x0001 },
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+ { 0x4061, 0x0002 },
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},
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}, {
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- 66000000, {
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- { 0x013e, 0x0003},
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- { 0x217e, 0x0002},
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- { 0x4061, 0x0002}
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+ 92000000, {
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+ { 0x0072, 0x0001 },
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+ { 0x2145, 0x0002 },
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+ { 0x4061, 0x0002 },
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},
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}, {
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- 74250000, {
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- { 0x0072, 0x0001},
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- { 0x2145, 0x0002},
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- { 0x4061, 0x0002}
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+ 122666000, {
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+ { 0x0051, 0x0002 },
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+ { 0x2145, 0x0002 },
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+ { 0x4061, 0x0002 },
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},
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}, {
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- 83500000, {
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- { 0x0072, 0x0001},
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+ 147200000, {
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+ { 0x0051, 0x0002 },
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+ { 0x2145, 0x0002 },
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+ { 0x4064, 0x0003 },
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},
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}, {
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- 108000000, {
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- { 0x0051, 0x0002},
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- { 0x2145, 0x0002},
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- { 0x4061, 0x0002}
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+ 184000000, {
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+ { 0x0051, 0x0002 },
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+ { 0x214c, 0x0003 },
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+ { 0x4064, 0x0003 },
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},
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}, {
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- 106500000, {
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- { 0x0051, 0x0002},
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- { 0x2145, 0x0002},
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- { 0x4061, 0x0002}
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- },
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- }, {
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- 146250000, {
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- { 0x0051, 0x0002},
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- { 0x2145, 0x0002},
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- { 0x4061, 0x0002}
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+ 226666000, {
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+ { 0x0040, 0x0003 },
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+ { 0x214c, 0x0003 },
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+ { 0x4064, 0x0003 },
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},
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}, {
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- 148500000, {
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- { 0x0051, 0x0003},
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- { 0x214c, 0x0003},
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- { 0x4064, 0x0003}
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+ 272000000, {
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+ { 0x0040, 0x0003 },
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+ { 0x214c, 0x0003 },
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+ { 0x5a64, 0x0003 },
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},
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}, {
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340000000, {
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@@ -168,10 +164,16 @@ static const struct dw_hdmi_mpll_config
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{ 0x5a64, 0x0003 },
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},
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}, {
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+ 600000000, {
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+ { 0x1a40, 0x0003 },
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+ { 0x3b4c, 0x0003 },
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+ { 0x5a64, 0x0003 },
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+ },
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+ }, {
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~0UL, {
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- { 0x00a0, 0x000a },
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- { 0x2001, 0x000f },
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- { 0x4002, 0x000f },
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+ { 0x0000, 0x0000 },
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+ { 0x0000, 0x0000 },
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+ { 0x0000, 0x0000 },
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},
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}
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};
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@@ -179,20 +181,6 @@ static const struct dw_hdmi_mpll_config
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static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
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/* pixelclk bpp8 bpp10 bpp12 */
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{
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- 40000000, { 0x0018, 0x0018, 0x0018 },
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- }, {
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- 65000000, { 0x0028, 0x0028, 0x0028 },
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- }, {
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- 66000000, { 0x0038, 0x0038, 0x0038 },
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- }, {
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- 74250000, { 0x0028, 0x0038, 0x0038 },
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- }, {
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- 83500000, { 0x0028, 0x0038, 0x0038 },
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- }, {
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- 146250000, { 0x0038, 0x0038, 0x0038 },
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- }, {
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- 148500000, { 0x0000, 0x0038, 0x0038 },
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- }, {
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600000000, { 0x0000, 0x0000, 0x0000 },
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}, {
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~0UL, { 0x0000, 0x0000, 0x0000},
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@@ -204,6 +192,7 @@ static const struct dw_hdmi_phy_config r
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{ 74250000, 0x8009, 0x0004, 0x0272},
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{ 148500000, 0x802b, 0x0004, 0x028d},
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{ 297000000, 0x8039, 0x0005, 0x028d},
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+ { 594000000, 0x8039, 0x0000, 0x019d},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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@@ -249,42 +238,6 @@ static int rockchip_hdmi_parse_dt(struct
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return 0;
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}
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-static enum drm_mode_status
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-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
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- const struct drm_display_info *info,
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- const struct drm_display_mode *mode)
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-{
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- struct rockchip_hdmi *hdmi = data;
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- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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- int pclk = mode->clock * 1000;
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- bool exact_match = hdmi->plat_data->phy_force_vendor;
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- int i;
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-
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- if (hdmi->ref_clk) {
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- int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
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-
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- if (abs(rpclk - pclk) > pclk / 1000)
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- return MODE_NOCLOCK;
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- }
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-
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- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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- /*
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- * For vendor specific phys force an exact match of the pixelclock
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- * to preserve the original behaviour of the driver.
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- */
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- if (exact_match && pclk == mpll_cfg[i].mpixelclock)
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- return MODE_OK;
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- /*
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- * The Synopsys phy can work with pixelclocks up to the value given
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- * in the corresponding mpll_cfg entry.
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- */
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- if (!exact_match && pclk <= mpll_cfg[i].mpixelclock)
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- return MODE_OK;
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- }
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-
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- return MODE_BAD;
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-}
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-
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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{
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}
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@@ -450,7 +403,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -467,7 +419,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -487,7 +438,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -505,7 +455,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -518,7 +467,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -625,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct
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}
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if (hdmi->chip_data == &rk3568_chip_data) {
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+ regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
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+ HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
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+ RK3568_HDMI_SCLIN_MSK,
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+ RK3568_HDMI_SDAIN_MSK |
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+ RK3568_HDMI_SCLIN_MSK));
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+ }
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+
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+ if (hdmi->chip_data == &rk3568_chip_data) {
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regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
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HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
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RK3568_HDMI_SCLIN_MSK,
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--- a/drivers/usb/dwc3/dwc3-of-simple.c
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+++ b/drivers/usb/dwc3/dwc3-of-simple.c
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@@ -30,12 +30,18 @@ struct dwc3_of_simple {
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bool need_reset;
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};
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+struct dwc3_of_simple_data {
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+ bool need_reset;
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+};
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+
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static int dwc3_of_simple_probe(struct platform_device *pdev)
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{
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struct dwc3_of_simple *simple;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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+ const struct dwc3_of_simple_data *data = of_device_get_match_data(dev);
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+
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int ret;
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simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
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@@ -49,8 +55,8 @@ static int dwc3_of_simple_probe(struct p
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* Some controllers need to toggle the usb3-otg reset before trying to
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* initialize the PHY, otherwise the PHY times out.
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*/
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- if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
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- simple->need_reset = true;
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+ if (data->need_reset)
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+ simple->need_reset = data->need_reset;
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simple->resets = of_reset_control_array_get(np, false, true,
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true);
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@@ -168,12 +174,34 @@ static const struct dev_pm_ops dwc3_of_s
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dwc3_of_simple_runtime_resume, NULL)
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};
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+static const struct dwc3_of_simple_data dwc3_of_simple_data_rk3399 = {
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+ .need_reset = true,
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+};
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+
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static const struct of_device_id of_dwc3_simple_match[] = {
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- { .compatible = "rockchip,rk3399-dwc3" },
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- { .compatible = "sprd,sc9860-dwc3" },
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- { .compatible = "allwinner,sun50i-h6-dwc3" },
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- { .compatible = "hisilicon,hi3670-dwc3" },
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- { .compatible = "intel,keembay-dwc3" },
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+ {
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+ .compatible = "allwinner,sun50i-h6-dwc3",
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+ },
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+ {
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+ .compatible = "cavium,octeon-7130-usb-uctl",
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+ },
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+ {
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+ .compatible = "hisilicon,hi3670-dwc3",
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+ },
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+ {
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+ .compatible = "intel,keembay-dwc3",
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+ },
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+ {
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+ .compatible = "rockchip,rk3399-dwc3",
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+ .data = &dwc3_of_simple_data_rk3399,
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+ },
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+ {
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+ .compatible = "rockchip,rk3568-dwc3",
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+ .data = &dwc3_of_simple_data_rk3399,
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+ },
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+ {
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+ .compatible = "sprd,sc9860-dwc3",
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+ },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
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--- a/kernel/dma/pool.c
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+++ b/kernel/dma/pool.c
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@@ -191,11 +191,10 @@ static int __init dma_atomic_pool_init(v
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/*
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* If coherent_pool was not used on the command line, default the pool
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* sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER.
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+ * Use 2MiB as default pool size.
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*/
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if (!atomic_pool_size) {
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- unsigned long pages = totalram_pages() / (SZ_1G / SZ_128K);
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- pages = min_t(unsigned long, pages, MAX_ORDER_NR_PAGES);
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- atomic_pool_size = max_t(size_t, pages << PAGE_SHIFT, SZ_128K);
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+ atomic_pool_size = SZ_2M;
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}
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INIT_WORK(&atomic_pool_work, atomic_pool_work_fn);
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--- a/sound/soc/codecs/rt5651.c
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+++ b/sound/soc/codecs/rt5651.c
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@@ -24,6 +24,7 @@
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/jack.h>
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+#include <linux/clk.h>
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#include "rl6231.h"
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#include "rt5651.h"
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@@ -1511,6 +1512,7 @@ static int rt5651_set_dai_pll(struct snd
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static int rt5651_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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+ struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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switch (level) {
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case SND_SOC_BIAS_PREPARE:
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if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
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@@ -1518,6 +1520,13 @@ static int rt5651_set_bias_level(struct
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snd_soc_component_update_bits(component, RT5651_D_MISC,
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0xc00, 0xc00);
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}
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+ if (!IS_ERR(rt5651->mclk)){
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+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
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+ clk_disable_unprepare(rt5651->mclk);
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+ } else {
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+ clk_prepare_enable(rt5651->mclk);
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+ }
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+ }
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break;
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case SND_SOC_BIAS_STANDBY:
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if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
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@@ -2059,6 +2068,13 @@ static int rt5651_probe(struct snd_soc_c
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{
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struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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+ /* Check if MCLK provided */
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+ rt5651->mclk = devm_clk_get(component->dev, "mclk");
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+ if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
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+ dev_err(component->dev, "unable to get mclk\n");
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+ return -EPROBE_DEFER;
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+ }
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+
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rt5651->component = component;
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snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
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--- a/sound/soc/codecs/rt5651.h
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+++ b/sound/soc/codecs/rt5651.h
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@@ -2097,6 +2097,7 @@ struct rt5651_priv {
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int dmic_en;
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bool hp_mute;
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+ struct clk *mclk;
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};
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#endif /* __RT5651_H__ */
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