384 lines
10 KiB
Diff
384 lines
10 KiB
Diff
From 7592a44966f7c135d4460b564fcd8d39fe323b68 Mon Sep 17 00:00:00 2001
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From: sbwml <984419930@qq.com>
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Date: Sat, 31 Dec 2022 18:42:34 +0800
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Subject: [PATCH] add hwrng for rk3568
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---
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.../bindings/rng/rockchip,rk3568-rng.yaml | 60 +++++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +
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drivers/char/hw_random/Kconfig | 14 +
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drivers/char/hw_random/Makefile | 1 +
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drivers/char/hw_random/rk3568-rng.c | 250 ++++++++++++++++++
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5 files changed, 335 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
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create mode 100644 drivers/char/hw_random/rk3568-rng.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3568-rng.yaml
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@@ -0,0 +1,60 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/rng/rockchip,rk3568-rng.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Rockchip TRNG
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+
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+description: True Random Number Generator for some Rockchip SoCs
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+
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+maintainers:
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+ - Aurelien Jarno <aurelien@aurel32.net>
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+
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+properties:
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+ compatible:
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+ enum:
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+ - rockchip,rk3568-rng
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: TRNG clock
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+ - description: TRNG AHB clock
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+
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+ clock-names:
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+ items:
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+ - const: trng_clk
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+ - const: trng_hclk
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+
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+ resets:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/rk3568-cru.h>
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+ bus {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ rng@fe388000 {
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+ compatible = "rockchip,rk3568-rng";
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+ reg = <0x0 0xfe388000 0x0 0x4000>;
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+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
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+ clock-names = "trng_clk", "trng_hclk";
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+ resets = <&cru SRST_TRNG_NS>;
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+ };
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+ };
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+
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+...
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -1806,6 +1806,16 @@
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};
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};
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+ rng: rng@fe388000 {
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+ compatible = "rockchip,rk3568-rng";
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+ reg = <0x0 0xfe388000 0x0 0x4000>;
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+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
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+ clock-names = "trng_clk", "trng_hclk";
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+ resets = <&cru SRST_TRNG_NS>;
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+ reset-names = "reset";
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+ status = "disabled";
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+ };
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+
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pinctrl: pinctrl {
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compatible = "rockchip,rk3568-pinctrl";
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rockchip,grf = <&grf>;
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--- a/drivers/char/hw_random/Kconfig
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+++ b/drivers/char/hw_random/Kconfig
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@@ -383,6 +383,20 @@ config HW_RANDOM_STM32
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If unsure, say N.
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+config HW_RANDOM_ROCKCHIP_RK3568
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+ tristate "Rockchip RK3568 True Random Number Generator"
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+ depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
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+ depends on HAS_IOMEM
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+ default HW_RANDOM
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+ help
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+ This driver provides kernel-side support for the True Random Number
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+ Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
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+
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+ To compile this driver as a module, choose M here: the
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+ module will be called rockchip-rng.
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+
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+ If unsure, say Y.
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+
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config HW_RANDOM_PIC32
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tristate "Microchip PIC32 Random Number Generator support"
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depends on MACH_PIC32 || COMPILE_TEST
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--- a/drivers/char/hw_random/Makefile
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+++ b/drivers/char/hw_random/Makefile
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@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
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obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
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obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
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obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
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+obj-$(CONFIG_HW_RANDOM_ROCKCHIP_RK3568) += rk3568-rng.o
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obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
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obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
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obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
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--- /dev/null
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+++ b/drivers/char/hw_random/rk3568-rng.c
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@@ -0,0 +1,250 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
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+ *
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+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
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+ * Copyright (c) 2022, Aurelien Jarno
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+ * Authors:
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+ * Lin Jinhan <troy.lin@rock-chips.com>
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+ * Aurelien Jarno <aurelien@aurel32.net>
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+ */
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+#include <linux/clk.h>
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+#include <linux/hw_random.h>
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+#include <linux/io.h>
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+#include <linux/iopoll.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/of_platform.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/reset.h>
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+#include <linux/slab.h>
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+
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+#define RK_RNG_AUTOSUSPEND_DELAY 100
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+#define RK_RNG_MAX_BYTE 32
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+#define RK_RNG_POLL_PERIOD_US 100
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+#define RK_RNG_POLL_TIMEOUT_US 10000
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+
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+/*
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+ * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
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+ * a tradeoff between speed and quality and has been adjusted to get a quality
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+ * of ~900 (~90% of FIPS 140-2 successes).
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+ */
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+#define RK_RNG_SAMPLE_CNT 1000
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+
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+/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
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+#define TRNG_RST_CTL 0x0004
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+#define TRNG_RNG_CTL 0x0400
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+#define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4)
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+#define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4)
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+#define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4)
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+#define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4)
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+#define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2)
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+#define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2)
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+#define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2)
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+#define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2)
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+#define TRNG_RNG_CTL_ENABLE BIT(1)
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+#define TRNG_RNG_CTL_START BIT(0)
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+#define TRNG_RNG_SAMPLE_CNT 0x0404
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+#define TRNG_RNG_DOUT_0 0x0410
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+#define TRNG_RNG_DOUT_1 0x0414
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+#define TRNG_RNG_DOUT_2 0x0418
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+#define TRNG_RNG_DOUT_3 0x041c
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+#define TRNG_RNG_DOUT_4 0x0420
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+#define TRNG_RNG_DOUT_5 0x0424
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+#define TRNG_RNG_DOUT_6 0x0428
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+#define TRNG_RNG_DOUT_7 0x042c
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+
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+struct rk_rng {
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+ struct hwrng rng;
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+ void __iomem *base;
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+ struct reset_control *rst;
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+ int clk_num;
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+ struct clk_bulk_data *clk_bulks;
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+};
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+
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+/* The mask determine the bits that are updated */
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+static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
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+{
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+ writel_relaxed((mask << 16) | val, rng->base + TRNG_RNG_CTL);
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+}
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+
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+static int rk_rng_init(struct hwrng *rng)
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+{
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+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+ u32 reg;
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+ int ret;
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+
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+ /* start clocks */
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+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
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+ if (ret < 0) {
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+ dev_err((struct device *) rk_rng->rng.priv,
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+ "Failed to enable clks %d\n", ret);
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+ return ret;
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+ }
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+
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+ /* set the sample period */
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+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
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+
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+ /* set osc ring speed and enable it */
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+ reg = TRNG_RNG_CTL_LEN_256_BIT |
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+ TRNG_RNG_CTL_OSC_RING_SPEED_0 |
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+ TRNG_RNG_CTL_ENABLE;
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+ rk_rng_write_ctl(rk_rng, reg, 0xffff);
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+
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+ return 0;
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+}
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+
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+static void rk_rng_cleanup(struct hwrng *rng)
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+{
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+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+ u32 reg;
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+
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+ /* stop TRNG */
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+ reg = 0;
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+ rk_rng_write_ctl(rk_rng, reg, 0xffff);
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+
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+ /* stop clocks */
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+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
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+}
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+
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+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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+{
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+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
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+ u32 reg;
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+ int ret = 0;
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+ int i;
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+
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+ pm_runtime_get_sync((struct device *) rk_rng->rng.priv);
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+
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+ /* Start collecting random data */
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+ reg = TRNG_RNG_CTL_START;
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+ rk_rng_write_ctl(rk_rng, reg, reg);
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+
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+ ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
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+ !(reg & TRNG_RNG_CTL_START),
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+ RK_RNG_POLL_PERIOD_US,
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+ RK_RNG_POLL_TIMEOUT_US);
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+ if (ret < 0)
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+ goto out;
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+
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+ /* Read random data stored in the registers */
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+ ret = min_t(size_t, max, RK_RNG_MAX_BYTE);
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+ for (i = 0; i < ret; i += 4) {
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+ *(u32 *)(buf + i) = readl_relaxed(rk_rng->base + TRNG_RNG_DOUT_0 + i);
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+ }
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+
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+out:
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+ pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
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+ pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
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+
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+ return ret;
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+}
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+
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+static int rk_rng_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct rk_rng *rk_rng;
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+ int ret;
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+
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+ rk_rng = devm_kzalloc(dev, sizeof(struct rk_rng), GFP_KERNEL);
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+ if (!rk_rng)
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+ return -ENOMEM;
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+
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+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(rk_rng->base))
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+ return PTR_ERR(rk_rng->base);
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+
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+ rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
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+ if (rk_rng->clk_num < 0)
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+ return dev_err_probe(dev, rk_rng->clk_num,
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+ "Failed to get clks property\n");
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+
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+ rk_rng->rst = devm_reset_control_array_get(&pdev->dev, false, false);
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+ if (IS_ERR(rk_rng->rst))
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+ return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
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+ "Failed to get reset property\n");
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+
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+ reset_control_assert(rk_rng->rst);
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+ udelay(2);
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+ reset_control_deassert(rk_rng->rst);
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+
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+ platform_set_drvdata(pdev, rk_rng);
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+
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+ rk_rng->rng.name = dev_driver_string(dev);
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+#ifndef CONFIG_PM
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+ rk_rng->rng.init = rk_rng_init;
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+ rk_rng->rng.cleanup = rk_rng_cleanup;
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+#endif
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+ rk_rng->rng.read = rk_rng_read;
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+ rk_rng->rng.priv = (unsigned long) dev;
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+ rk_rng->rng.quality = 900;
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+
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+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
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+ pm_runtime_use_autosuspend(dev);
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+ pm_runtime_enable(dev);
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+
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+ ret = devm_hwrng_register(dev, &rk_rng->rng);
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+ if (ret)
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+ return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
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+
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+ dev_info(&pdev->dev, "Registered Rockchip hwrng\n");
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+
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+ return 0;
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+}
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+
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+static int rk_rng_remove(struct platform_device *pdev)
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+{
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+ pm_runtime_disable(&pdev->dev);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM
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+static int rk_rng_runtime_suspend(struct device *dev)
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+{
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+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
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+
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+ rk_rng_cleanup(&rk_rng->rng);
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+
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+ return 0;
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+}
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+
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+static int rk_rng_runtime_resume(struct device *dev)
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+{
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+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
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+
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+ return rk_rng_init(&rk_rng->rng);
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+}
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+#endif
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+
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+static const struct dev_pm_ops rk_rng_pm_ops = {
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+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
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+ rk_rng_runtime_resume, NULL)
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+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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+ pm_runtime_force_resume)
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+};
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+
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+static const struct of_device_id rk_rng_dt_match[] = {
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+ {
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+ .compatible = "rockchip,rk3568-rng",
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+ },
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+ {},
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+};
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+
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+MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
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+
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+static struct platform_driver rk_rng_driver = {
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+ .driver = {
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+ .name = "rk3568-rng",
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+ .pm = &rk_rng_pm_ops,
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+ .of_match_table = rk_rng_dt_match,
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+ },
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+ .probe = rk_rng_probe,
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+ .remove = rk_rng_remove,
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+};
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+
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+module_platform_driver(rk_rng_driver);
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+
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+MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
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+MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>, Aurelien Jarno <aurelien@aurel32.net>");
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+MODULE_LICENSE("GPL v2");
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