41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
From e0606b7dac4764ef7d7cd07dbb127913a01cf0bb Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Wed, 24 May 2023 10:31:39 +0200
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Subject: [PATCH 399/414] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
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According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
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set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
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at it turn the if/else if/else into switch/case which makes it easier
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to read.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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---
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drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -82,12 +82,19 @@ static void rockchip_dfi_start_hardware_
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DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
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/* set ddr type to dfi */
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- if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
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+ switch (dfi->ddr_type) {
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+ case ROCKCHIP_DDRTYPE_LPDDR2:
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+ case ROCKCHIP_DDRTYPE_LPDDR3:
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writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
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dfi_regs + DDRMON_CTRL);
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- else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
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+ break;
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+ case ROCKCHIP_DDRTYPE_LPDDR4:
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writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
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dfi_regs + DDRMON_CTRL);
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+ break;
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+ default:
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+ break;
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+ }
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/* enable count, use software mode */
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writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
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