138 lines
4.1 KiB
Diff
138 lines
4.1 KiB
Diff
From 69dbc52aef08f566494ae5da340dc708c3f3e362 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Wed, 24 May 2023 10:31:46 +0200
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Subject: [PATCH 406/414] PM / devfreq: rockchip-dfi: account for multiple
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DDRMON_CTRL registers
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The currently supported RK3399 has a set of registers per channel, but
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it has only a single DDRMON_CTRL register. With upcoming RK3588 this
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will be different, the RK3588 has a DDRMON_CTRL register per channel.
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Instead of expecting a single DDRMON_CTRL register, loop over the
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channels and write the channel specific DDRMON_CTRL register. Break
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out early out of the loop when there is only a single DDRMON_CTRL
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register like on the RK3399.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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---
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drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++++++----------
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1 file changed, 48 insertions(+), 24 deletions(-)
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -113,12 +113,13 @@ struct rockchip_dfi {
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int burst_len;
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int buswidth[DMC_MAX_CHANNELS];
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int ddrmon_stride;
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+ bool ddrmon_ctrl_single;
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};
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static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
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{
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void __iomem *dfi_regs = dfi->regs;
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- int ret = 0;
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+ int i, ret = 0;
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mutex_lock(&dfi->mutex);
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@@ -132,29 +133,41 @@ static int rockchip_dfi_enable(struct ro
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goto out;
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}
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- /* clear DDRMON_CTRL setting */
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- writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
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- DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
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+ for (i = 0; i < DMC_MAX_CHANNELS; i++) {
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+ u32 ctrl = 0;
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- /* set ddr type to dfi */
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- switch (dfi->ddr_type) {
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- case ROCKCHIP_DDRTYPE_LPDDR2:
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- case ROCKCHIP_DDRTYPE_LPDDR3:
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- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
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- dfi_regs + DDRMON_CTRL);
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- break;
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- case ROCKCHIP_DDRTYPE_LPDDR4:
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- case ROCKCHIP_DDRTYPE_LPDDR4X:
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- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
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- dfi_regs + DDRMON_CTRL);
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- break;
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- default:
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- break;
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- }
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+ if (!(dfi->channel_mask & BIT(i)))
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+ continue;
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- /* enable count, use software mode */
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- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
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- dfi_regs + DDRMON_CTRL);
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+ /* clear DDRMON_CTRL setting */
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+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
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+ DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN),
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+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
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+
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+ /* set ddr type to dfi */
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+ switch (dfi->ddr_type) {
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+ case ROCKCHIP_DDRTYPE_LPDDR2:
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+ case ROCKCHIP_DDRTYPE_LPDDR3:
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+ ctrl = DDRMON_CTRL_LPDDR23;
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+ break;
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+ case ROCKCHIP_DDRTYPE_LPDDR4:
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+ case ROCKCHIP_DDRTYPE_LPDDR4X:
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+ ctrl = DDRMON_CTRL_LPDDR4;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
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+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
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+
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+ /* enable count, use software mode */
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+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
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+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
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+
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+ if (dfi->ddrmon_ctrl_single)
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+ break;
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+ }
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out:
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mutex_unlock(&dfi->mutex);
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@@ -164,6 +177,7 @@ out:
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static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
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{
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void __iomem *dfi_regs = dfi->regs;
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+ int i;
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mutex_lock(&dfi->mutex);
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@@ -174,8 +188,17 @@ static void rockchip_dfi_disable(struct
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if (dfi->usecount > 0)
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goto out;
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- writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
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- dfi_regs + DDRMON_CTRL);
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+ for (i = 0; i < DMC_MAX_CHANNELS; i++) {
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+ if (!(dfi->channel_mask & BIT(i)))
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+ continue;
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+
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+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
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+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
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+
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+ if (dfi->ddrmon_ctrl_single)
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+ break;
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+ }
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+
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clk_disable_unprepare(dfi->clk);
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out:
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mutex_unlock(&dfi->mutex);
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@@ -663,6 +686,7 @@ static int rk3399_dfi_init(struct rockch
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dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
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dfi->ddrmon_stride = 0x14;
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+ dfi->ddrmon_ctrl_single = true;
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return 0;
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};
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