57 lines
2.0 KiB
Diff
57 lines
2.0 KiB
Diff
From 1067b1854ad723a3cd57f76924fb3c7ddea6f22e Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Wed, 24 May 2023 10:31:45 +0200
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Subject: [PATCH 405/414] PM / devfreq: rockchip-dfi: make register stride SoC
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specific
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The currently supported RK3399 has a stride of 20 between the channel
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specific registers. Upcoming RK3588 has a different stride, so put
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the stride into driver data to make it configurable.
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While at it convert decimal 20 to hex 0x14 for consistency with RK3588
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which has a register stride 0x4000 and we want to write that in hex
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as well.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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---
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drivers/devfreq/event/rockchip-dfi.c | 11 +++++++----
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1 file changed, 7 insertions(+), 4 deletions(-)
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -112,6 +112,7 @@ struct rockchip_dfi {
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int active_events;
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int burst_len;
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int buswidth[DMC_MAX_CHANNELS];
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+ int ddrmon_stride;
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};
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static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
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@@ -189,13 +190,13 @@ static void rockchip_dfi_read_counters(s
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if (!(dfi->channel_mask & BIT(i)))
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continue;
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c->c[i].read_access = readl_relaxed(dfi_regs +
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- DDRMON_CH0_RD_NUM + i * 20);
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+ DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
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c->c[i].write_access = readl_relaxed(dfi_regs +
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- DDRMON_CH0_WR_NUM + i * 20);
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+ DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
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c->c[i].access = readl_relaxed(dfi_regs +
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- DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
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+ DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride);
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c->c[i].clock_cycles = readl_relaxed(dfi_regs +
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- DDRMON_CH0_COUNT_NUM + i * 20);
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+ DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
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}
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}
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@@ -661,6 +662,8 @@ static int rk3399_dfi_init(struct rockch
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dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
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dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
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+ dfi->ddrmon_stride = 0x14;
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+
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return 0;
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};
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