71 lines
2.6 KiB
Diff
71 lines
2.6 KiB
Diff
From 075a5b3969becb1ebc2f1d4fa1a1fe9163679273 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 11 Dec 2023 19:58:15 +0800
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Subject: [PATCH] drm/rockchip: vop2: set bg dly and prescan dly at
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vop2_post_config
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We need to setup background delay cycle and prescan
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delay cycle when a mode is enable to avoid trigger
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POST_BUF_EMPTY irq on rk3588.
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Note: RK356x has no such requirement.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://patchwork.freedesktop.org/patch/msgid/20231211115815.1785131-1-andyshrk@163.com
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---
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 ++++++++------------
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1 file changed, 10 insertions(+), 16 deletions(-)
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -1462,8 +1462,18 @@ static void vop2_post_config(struct drm_
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u32 top_margin = 100, bottom_margin = 100;
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u16 hsize = hdisplay * (left_margin + right_margin) / 200;
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u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
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+ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
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u16 hact_end, vact_end;
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u32 val;
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+ u32 bg_dly;
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+ u32 pre_scan_dly;
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+
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+ bg_dly = vp->data->pre_scan_max_dly[3];
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+ vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
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+ FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
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+
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+ pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
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+ vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
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vsize = rounddown(vsize, 2);
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hsize = rounddown(hsize, 2);
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@@ -1958,11 +1968,6 @@ static void vop2_setup_layer_mixer(struc
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u32 layer_sel = 0;
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u32 port_sel;
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unsigned int nlayer, ofs;
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- struct drm_display_mode *adjusted_mode;
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- u16 hsync_len;
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- u16 hdisplay;
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- u32 bg_dly;
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- u32 pre_scan_dly;
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u32 ovl_ctrl;
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int i;
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struct vop2_video_port *vp0 = &vop2->vps[0];
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@@ -1970,17 +1975,6 @@ static void vop2_setup_layer_mixer(struc
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struct vop2_video_port *vp2 = &vop2->vps[2];
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struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
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- adjusted_mode = &vp->crtc.state->adjusted_mode;
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- hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
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- hdisplay = adjusted_mode->crtc_hdisplay;
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-
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- bg_dly = vp->data->pre_scan_max_dly[3];
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- vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
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- FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
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-
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- pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
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- vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
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-
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ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
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ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
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if (vcstate->yuv_overlay)
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