177 lines
3.5 KiB
Plaintext
177 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include "rk3568-nanopi-common.dtsi"
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/ {
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model = "FriendlyElec NanoPi R5S";
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compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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cooling-levels = <0 18 60 100 255>;
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#cooling-cells = <2>;
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fan-supply = <&vcc5v0_sysp>;
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pwms = <&pwm0 0 50000 0>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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sys_led: led-sys {
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gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
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label = "red:power";
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linux,default-trigger = "heartbeat";
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pinctrl-names = "default";
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pinctrl-0 = <&sys_led_pin>;
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};
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wan_led: led-wan {
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gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
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label = "green:wan";
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pinctrl-names = "default";
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pinctrl-0 = <&wan_led_pin>;
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};
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lan1_led: led-lan1 {
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gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
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label = "green:lan1";
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pinctrl-names = "default";
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pinctrl-0 = <&lan1_led_pin>;
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};
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lan2_led: led-lan2 {
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gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
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label = "green:lan2";
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pinctrl-names = "default";
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pinctrl-0 = <&lan2_led_pin>;
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};
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};
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
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assigned-clock-rates = <0>, <125000000>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy0>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 15ms, 50ms for rtl8211f */
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snps,reset-delays-us = <0 15000 50000>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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status = "okay";
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};
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&mdio0 {
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rgmii_phy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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pinctrl-0 = <ð_phy0_reset_pin>;
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pinctrl-names = "default";
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realtek,led-data = <0x6d60>;
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};
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};
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&pcie2x1 {
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num-lanes = <1>;
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reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pcie@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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rtl8125_1: pcie@1,0 {
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compatible = "pci10ec,8125";
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reg = <0x000000 0 0 0 0>;
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realtek,led-data = <0x0 0x0 0x2b 0x200>;
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};
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};
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};
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&pcie30phy {
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data-lanes = <1 2>;
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status = "okay";
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};
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&pcie3x1 {
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num-lanes = <1>;
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reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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pcie@0,0 {
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reg = <0x00100000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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rtl8125_2: pcie@10,0 {
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compatible = "pci10ec,8125";
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reg = <0x000000 0 0 0 0>;
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realtek,led-data = <0x0 0x0 0x2b 0x200>;
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};
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};
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};
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&pcie3x2 {
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num-lanes = <1>;
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num-ib-windows = <8>;
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num-ob-windows = <8>;
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reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pinctrl {
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gmac0 {
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eth_phy0_reset_pin: eth-phy0-reset-pin {
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rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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gpio-leds {
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sys_led_pin: sys-led-pin {
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rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wan_led_pin: wan-led-pin {
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rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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lan1_led_pin: lan1-led-pin {
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rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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lan2_led_pin: lan2-led-pin {
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rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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gpio-key {
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key1_pin: key1-pin {
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rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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&pwm0 {
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status = "okay";
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};
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