rockchip: switch linux-6.6

Signed-off-by: sbwml <admin@cooluc.com>

Makefile

@@ -7,7 +7,7 @@ BOARDNAME:=Rockchip
 FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
 SUBTARGETS:=armv8
 
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
 
 define Target/Description
 	Build firmware image for Rockchip SoC devices.

armv8/config-6.6

@@ -117,6 +117,7 @@ CONFIG_CLK_RK3328=y
 CONFIG_CLK_RK3368=y
 CONFIG_CLK_RK3399=y
 CONFIG_CLK_RK3568=y
+# CONFIG_CLK_RK3588 is not set
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_CMA=y
 CONFIG_CMA_ALIGNMENT=8
@@ -396,6 +397,8 @@ CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_CORE=y
 # CONFIG_MFD_KHADAS_MCU is not set
 CONFIG_MFD_RK808=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MMC=y

patches-6.1/004-arm64-add-dts-rk3568-nanopi-r5s.patch

@@ -1,9 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -71,4 +71,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb

patches-6.1/212-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch

@@ -1,59 +0,0 @@
-From 59e0ec5e5916ed4fac238a3da39aa0659831c41c Mon Sep 17 00:00:00 2001
-From: Heiko Stuebner <heiko@sntech.de>
-Date: Sun, 30 Oct 2022 20:34:42 +0100
-Subject: [PATCH 6/7] arm64: dts: rockchip: fix spdif@fe460000 ordering on
- rk356x
-
-Move the node to its correct position, based on its
-mmio-address.
-
-Link: https://lore.kernel.org/all/20221030193708.1671069-1-heiko@sntech.de
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++------------
- 1 file changed, 14 insertions(+), 14 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1060,20 +1060,6 @@
- 		status = "disabled";
- 	};
- 
--	spdif: spdif@fe460000 {
--		compatible = "rockchip,rk3568-spdif";
--		reg = <0x0 0xfe460000 0x0 0x1000>;
--		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
--		clock-names = "mclk", "hclk";
--		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
--		dmas = <&dmac1 1>;
--		dma-names = "tx";
--		pinctrl-names = "default";
--		pinctrl-0 = <&spdifm0_tx>;
--		#sound-dai-cells = <0>;
--		status = "disabled";
--	};
--
- 	i2s0_8ch: i2s@fe400000 {
- 		compatible = "rockchip,rk3568-i2s-tdm";
- 		reg = <0x0 0xfe400000 0x0 0x1000>;
-@@ -1152,6 +1138,20 @@
- 		#sound-dai-cells = <0>;
- 		status = "disabled";
- 	};
-+
-+	spdif: spdif@fe460000 {
-+		compatible = "rockchip,rk3568-spdif";
-+		reg = <0x0 0xfe460000 0x0 0x1000>;
-+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-+		clock-names = "mclk", "hclk";
-+		clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
-+		dmas = <&dmac1 1>;
-+		dma-names = "tx";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&spdifm0_tx>;
-+		#sound-dai-cells = <0>;
-+		status = "disabled";
-+	};
- 
- 	dmac0: dma-controller@fe530000 {
- 		compatible = "arm,pl330", "arm,primecell";

patches-6.1/213-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch

@@ -1,45 +0,0 @@
-From 6c51234cd4e1bfd637c3aab0a94893e832670fe5 Mon Sep 17 00:00:00 2001
-From: Shengyu Qu <wiagn233@outlook.com>
-Date: Sun, 30 Oct 2022 01:09:04 +0800
-Subject: [PATCH 7/7] arm64: dts: rockchip: RK356x: Add I2S2 device node
-
-This patch adds I2S2 device tree node for RK3566/RK3568.
-
-Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
-Link: https://lore.kernel.org/r/OS3P286MB259771C12F2B15A4DDF435FE98359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1102,6 +1102,28 @@
- 		status = "disabled";
- 	};
- 
-+	i2s2_2ch: i2s@fe420000 {
-+		compatible = "rockchip,rk3568-i2s-tdm";
-+		reg = <0x0 0xfe420000 0x0 0x1000>;
-+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-+		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
-+		assigned-clock-rates = <1188000000>;
-+		clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
-+		clock-names = "mclk_tx", "mclk_rx", "hclk";
-+		dmas = <&dmac1 4>, <&dmac1 5>;
-+		dma-names = "tx", "rx";
-+		resets = <&cru SRST_M_I2S2_2CH>;
-+		reset-names = "m";
-+		rockchip,grf = <&grf>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&i2s2m0_sclktx
-+				&i2s2m0_lrcktx
-+				&i2s2m0_sdi
-+				&i2s2m0_sdo>;
-+		#sound-dai-cells = <0>;
-+		status = "disabled";
-+	};
-+
- 	i2s3_2ch: i2s@fe430000 {
- 		compatible = "rockchip,rk3568-i2s-tdm";
- 		reg = <0x0 0xfe430000 0x0 0x1000>;

patches-6.6/002-add-hwrng-for-rk3568.patch

@@ -78,7 +78,7 @@ Subject: [PATCH] add hwrng for rk3568
 +...
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1772,6 +1772,16 @@
+@@ -1806,6 +1806,16 @@
  		};
  	};
  
@@ -97,7 +97,7 @@ Subject: [PATCH] add hwrng for rk3568
  		rockchip,grf = <&grf>;
 --- a/drivers/char/hw_random/Kconfig
 +++ b/drivers/char/hw_random/Kconfig
-@@ -372,6 +372,20 @@ config HW_RANDOM_STM32
+@@ -383,6 +383,20 @@ config HW_RANDOM_STM32
  
  	  If unsure, say N.
  
@@ -117,10 +117,10 @@ Subject: [PATCH] add hwrng for rk3568
 +
  config HW_RANDOM_PIC32
  	tristate "Microchip PIC32 Random Number Generator support"
- 	depends on HW_RANDOM && MACH_PIC32
+ 	depends on MACH_PIC32 || COMPILE_TEST
 --- a/drivers/char/hw_random/Makefile
 +++ b/drivers/char/hw_random/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
+@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
  obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
  obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
  obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o

patches-6.6/003-rk3568-general-patch-set.patch

@@ -9,9 +9,277 @@
  	struct clk_mux *mux = NULL;
  	struct clk_gate *gate = NULL;
  	struct clk_divider *div = NULL;
+--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+@@ -92,74 +92,70 @@ static struct rockchip_hdmi *to_rockchip
+ 
+ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
+ 	{
+-		27000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		30666000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40f3, 0x0000 },
+ 		},
+ 	}, {
+-		36000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		36800000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2153, 0x0000 },
++			{ 0x40a2, 0x0001 },
+ 		},
+ 	}, {
+-		40000000, {
+-			{ 0x00b3, 0x0000},
+-			{ 0x2153, 0x0000},
+-			{ 0x40f3, 0x0000}
++		46000000, {
++			{ 0x00b3, 0x0000 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+ 	}, {
+-		54000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++		61333000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x40a2, 0x0001 },
+ 		},
+ 	}, {
+-		65000000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2142, 0x0001},
+-			{ 0x40a2, 0x0001},
++		73600000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2142, 0x0001 },
++			{ 0x4061, 0x0002 },
+ 		},
+ 	}, {
+-		66000000, {
+-			{ 0x013e, 0x0003},
+-			{ 0x217e, 0x0002},
+-			{ 0x4061, 0x0002}
++		92000000, {
++			{ 0x0072, 0x0001 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+ 	}, {
+-		74250000, {
+-			{ 0x0072, 0x0001},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++		122666000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4061, 0x0002 },
+ 		},
+ 	}, {
+-		83500000, {
+-			{ 0x0072, 0x0001},
++		147200000, {
++			{ 0x0051, 0x0002 },
++			{ 0x2145, 0x0002 },
++			{ 0x4064, 0x0003 },
+ 		},
+ 	}, {
+-		108000000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++		184000000, {
++			{ 0x0051, 0x0002 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+ 	}, {
+-		106500000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
+-		},
+-	}, {
+-		146250000, {
+-			{ 0x0051, 0x0002},
+-			{ 0x2145, 0x0002},
+-			{ 0x4061, 0x0002}
++		226666000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x4064, 0x0003 },
+ 		},
+ 	}, {
+-		148500000, {
+-			{ 0x0051, 0x0003},
+-			{ 0x214c, 0x0003},
+-			{ 0x4064, 0x0003}
++		272000000, {
++			{ 0x0040, 0x0003 },
++			{ 0x214c, 0x0003 },
++			{ 0x5a64, 0x0003 },
+ 		},
+ 	}, {
+ 		340000000, {
+@@ -168,10 +164,16 @@ static const struct dw_hdmi_mpll_config
+ 			{ 0x5a64, 0x0003 },
+ 		},
+ 	}, {
++		600000000, {
++			{ 0x1a40, 0x0003 },
++			{ 0x3b4c, 0x0003 },
++			{ 0x5a64, 0x0003 },
++ 		},
++	}, {
+ 		~0UL, {
+-			{ 0x00a0, 0x000a },
+-			{ 0x2001, 0x000f },
+-			{ 0x4002, 0x000f },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
++			{ 0x0000, 0x0000 },
+ 		},
+ 	}
+ };
+@@ -179,20 +181,6 @@ static const struct dw_hdmi_mpll_config
+ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
+ 	/*      pixelclk    bpp8    bpp10   bpp12 */
+ 	{
+-		40000000,  { 0x0018, 0x0018, 0x0018 },
+-	}, {
+-		65000000,  { 0x0028, 0x0028, 0x0028 },
+-	}, {
+-		66000000,  { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		74250000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		83500000,  { 0x0028, 0x0038, 0x0038 },
+-	}, {
+-		146250000, { 0x0038, 0x0038, 0x0038 },
+-	}, {
+-		148500000, { 0x0000, 0x0038, 0x0038 },
+-	}, {
+ 		600000000, { 0x0000, 0x0000, 0x0000 },
+ 	}, {
+ 		~0UL,      { 0x0000, 0x0000, 0x0000},
+@@ -204,6 +192,7 @@ static const struct dw_hdmi_phy_config r
+ 	{ 74250000,  0x8009, 0x0004, 0x0272},
+ 	{ 148500000, 0x802b, 0x0004, 0x028d},
+ 	{ 297000000, 0x8039, 0x0005, 0x028d},
++	{ 594000000, 0x8039, 0x0000, 0x019d},
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
+@@ -249,42 +238,6 @@ static int rockchip_hdmi_parse_dt(struct
+ 	return 0;
+ }
+ 
+-static enum drm_mode_status
+-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
+-			    const struct drm_display_info *info,
+-			    const struct drm_display_mode *mode)
+-{
+-	struct rockchip_hdmi *hdmi = data;
+-	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+-	int pclk = mode->clock * 1000;
+-	bool exact_match = hdmi->plat_data->phy_force_vendor;
+-	int i;
+-
+-	if (hdmi->ref_clk) {
+-		int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
+-
+-		if (abs(rpclk - pclk) > pclk / 1000)
+-			return MODE_NOCLOCK;
+-	}
+-
+-	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		/*
+-		 * For vendor specific phys force an exact match of the pixelclock
+-		 * to preserve the original behaviour of the driver.
+-		 */
+-		if (exact_match && pclk == mpll_cfg[i].mpixelclock)
+-			return MODE_OK;
+-		/*
+-		 * The Synopsys phy can work with pixelclocks up to the value given
+-		 * in the corresponding mpll_cfg entry.
+-		 */
+-		if (!exact_match && pclk <= mpll_cfg[i].mpixelclock)
+-			return MODE_OK;
+-	}
+-
+-	return MODE_BAD;
+-}
+-
+ static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
+ {
+ }
+@@ -450,7 +403,6 @@ static struct rockchip_hdmi_chip_data rk
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg = rockchip_mpll_cfg,
+ 	.cur_ctr = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -467,7 +419,6 @@ static struct rockchip_hdmi_chip_data rk
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -487,7 +438,6 @@ static struct rockchip_hdmi_chip_data rk
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg = rockchip_mpll_cfg,
+ 	.cur_ctr = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -505,7 +455,6 @@ static struct rockchip_hdmi_chip_data rk
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -518,7 +467,6 @@ static struct rockchip_hdmi_chip_data rk
+ };
+ 
+ static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
+-	.mode_valid = dw_hdmi_rockchip_mode_valid,
+ 	.mpll_cfg   = rockchip_mpll_cfg,
+ 	.cur_ctr    = rockchip_cur_ctr,
+ 	.phy_config = rockchip_phy_config,
+@@ -625,6 +573,14 @@ static int dw_hdmi_rockchip_bind(struct
+ 	}
+ 
+ 	if (hdmi->chip_data == &rk3568_chip_data) {
++		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
++			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK,
++					   RK3568_HDMI_SDAIN_MSK |
++					   RK3568_HDMI_SCLIN_MSK));
++	}
++
++	if (hdmi->chip_data == &rk3568_chip_data) {
+ 		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
+ 			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
+ 					   RK3568_HDMI_SCLIN_MSK,
 --- a/drivers/usb/dwc3/dwc3-of-simple.c
 +++ b/drivers/usb/dwc3/dwc3-of-simple.c
-@@ -30,12 +30,16 @@ struct dwc3_of_simple {
+@@ -30,12 +30,18 @@ struct dwc3_of_simple {
  	bool			need_reset;
  };
  
@@ -24,12 +292,13 @@
  	struct dwc3_of_simple	*simple;
  	struct device		*dev = &pdev->dev;
  	struct device_node	*np = dev->of_node;
--
+ 
-+	const struct dwc3_of_simple_data *data = of_device_get_match_data(dev);
++	const struct		dwc3_of_simple_data *data = of_device_get_match_data(dev);
++
  	int			ret;
  
  	simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
-@@ -49,8 +53,8 @@ static int dwc3_of_simple_probe(struct p
+@@ -49,8 +55,8 @@ static int dwc3_of_simple_probe(struct p
  	 * Some controllers need to toggle the usb3-otg reset before trying to
  	 * initialize the PHY, otherwise the PHY times out.
  	 */
@@ -40,7 +309,7 @@
  
  	simple->resets = of_reset_control_array_get(np, false, true,
  						    true);
-@@ -170,13 +174,34 @@ static const struct dev_pm_ops dwc3_of_s
+@@ -168,12 +174,34 @@ static const struct dev_pm_ops dwc3_of_s
  			dwc3_of_simple_runtime_resume, NULL)
  };
  
@@ -50,7 +319,6 @@
 +
  static const struct of_device_id of_dwc3_simple_match[] = {
 -	{ .compatible = "rockchip,rk3399-dwc3" },
--	{ .compatible = "cavium,octeon-7130-usb-uctl" },
 -	{ .compatible = "sprd,sc9860-dwc3" },
 -	{ .compatible = "allwinner,sun50i-h6-dwc3" },
 -	{ .compatible = "hisilicon,hi3670-dwc3" },
@@ -83,12 +351,10 @@
  MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
 --- a/kernel/dma/pool.c
 +++ b/kernel/dma/pool.c
-@@ -189,13 +189,10 @@ static int __init dma_atomic_pool_init(v
+@@ -191,11 +191,10 @@ static int __init dma_atomic_pool_init(v
- 	int ret = 0;
- 
  	/*
--	 * If coherent_pool was not used on the command line, default the pool
+ 	 * If coherent_pool was not used on the command line, default the pool
--	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER-1.
+ 	 * sizes to 128KB per 1GB of memory, min 128KB, max MAX_ORDER.
 +	 * Use 2MiB as default pool size.
  	 */
  	if (!atomic_pool_size) {
@@ -155,279 +421,3 @@
  };
  
  #endif /* __RT5651_H__ */
---- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
-+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
-@@ -91,80 +91,88 @@ static struct rockchip_hdmi *to_rockchip
- 
- static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
- 	{
--		27000000, {
--			{ 0x00b3, 0x0000},
--			{ 0x2153, 0x0000},
--			{ 0x40f3, 0x0000}
--		},
--	}, {
--		36000000, {
--			{ 0x00b3, 0x0000},
--			{ 0x2153, 0x0000},
--			{ 0x40f3, 0x0000}
--		},
--	}, {
--		40000000, {
--			{ 0x00b3, 0x0000},
--			{ 0x2153, 0x0000},
--			{ 0x40f3, 0x0000}
--		},
--	}, {
--		54000000, {
--			{ 0x0072, 0x0001},
--			{ 0x2142, 0x0001},
--			{ 0x40a2, 0x0001},
--		},
--	}, {
--		65000000, {
--			{ 0x0072, 0x0001},
--			{ 0x2142, 0x0001},
--			{ 0x40a2, 0x0001},
--		},
--	}, {
--		66000000, {
--			{ 0x013e, 0x0003},
--			{ 0x217e, 0x0002},
--			{ 0x4061, 0x0002}
--		},
--	}, {
--		74250000, {
--			{ 0x0072, 0x0001},
--			{ 0x2145, 0x0002},
--			{ 0x4061, 0x0002}
--		},
--	}, {
--		83500000, {
--			{ 0x0072, 0x0001},
--		},
--	}, {
--		108000000, {
--			{ 0x0051, 0x0002},
--			{ 0x2145, 0x0002},
--			{ 0x4061, 0x0002}
--		},
--	}, {
--		106500000, {
--			{ 0x0051, 0x0002},
--			{ 0x2145, 0x0002},
--			{ 0x4061, 0x0002}
--		},
--	}, {
--		146250000, {
--			{ 0x0051, 0x0002},
--			{ 0x2145, 0x0002},
--			{ 0x4061, 0x0002}
--		},
--	}, {
--		148500000, {
--			{ 0x0051, 0x0003},
--			{ 0x214c, 0x0003},
--			{ 0x4064, 0x0003}
-+		30666000, {
-+			{ 0x00b3, 0x0000 },
-+			{ 0x2153, 0x0000 },
-+			{ 0x40f3, 0x0000 },
-+		},
-+	},  {
-+		36800000, {
-+			{ 0x00b3, 0x0000 },
-+			{ 0x2153, 0x0000 },
-+			{ 0x40a2, 0x0001 },
-+		},
-+	},  {
-+		46000000, {
-+			{ 0x00b3, 0x0000 },
-+			{ 0x2142, 0x0001 },
-+			{ 0x40a2, 0x0001 },
-+		},
-+	},  {
-+		61333000, {
-+			{ 0x0072, 0x0001 },
-+			{ 0x2142, 0x0001 },
-+			{ 0x40a2, 0x0001 },
-+		},
-+	},  {
-+		73600000, {
-+			{ 0x0072, 0x0001 },
-+			{ 0x2142, 0x0001 },
-+			{ 0x4061, 0x0002 },
-+		},
-+	},  {
-+		92000000, {
-+			{ 0x0072, 0x0001 },
-+			{ 0x2145, 0x0002 },
-+			{ 0x4061, 0x0002 },
-+		},
-+	},  {
-+		122666000, {
-+			{ 0x0051, 0x0002 },
-+			{ 0x2145, 0x0002 },
-+			{ 0x4061, 0x0002 },
-+		},
-+	},  {
-+		147200000, {
-+			{ 0x0051, 0x0002 },
-+			{ 0x2145, 0x0002 },
-+			{ 0x4064, 0x0003 },
-+		},
-+	},  {
-+		184000000, {
-+			{ 0x0051, 0x0002 },
-+			{ 0x214c, 0x0003 },
-+			{ 0x4064, 0x0003 },
-+		},
-+	},  {
-+		226666000, {
-+			{ 0x0040, 0x0003 },
-+			{ 0x214c, 0x0003 },
-+			{ 0x4064, 0x0003 },
-+		},
-+	},  {
-+		272000000, {
-+			{ 0x0040, 0x0003 },
-+			{ 0x214c, 0x0003 },
-+			{ 0x5a64, 0x0003 },
-+		},
-+	},  {
-+		340000000, {
-+			{ 0x0040, 0x0003 },
-+			{ 0x3b4c, 0x0003 },
-+			{ 0x5a64, 0x0003 },
-+		},
-+	},  {
-+		600000000, {
-+			{ 0x1a40, 0x0003 },
-+			{ 0x3b4c, 0x0003 },
-+			{ 0x5a64, 0x0003 },
- 		},
--	}, {
-+	},  {
- 		~0UL, {
--			{ 0x00a0, 0x000a },
--			{ 0x2001, 0x000f },
--			{ 0x4002, 0x000f },
-+			{ 0x0000, 0x0000 },
-+			{ 0x0000, 0x0000 },
-+			{ 0x0000, 0x0000 },
- 		},
- 	}
- };
-@@ -172,20 +180,8 @@ static const struct dw_hdmi_mpll_config
- static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
- 	/*      pixelclk    bpp8    bpp10   bpp12 */
- 	{
--		40000000,  { 0x0018, 0x0018, 0x0018 },
--	}, {
--		65000000,  { 0x0028, 0x0028, 0x0028 },
--	}, {
--		66000000,  { 0x0038, 0x0038, 0x0038 },
--	}, {
--		74250000,  { 0x0028, 0x0038, 0x0038 },
--	}, {
--		83500000,  { 0x0028, 0x0038, 0x0038 },
--	}, {
--		146250000, { 0x0038, 0x0038, 0x0038 },
--	}, {
--		148500000, { 0x0000, 0x0038, 0x0038 },
--	}, {
-+		600000000, { 0x0000, 0x0000, 0x0000 },
-+	},  {
- 		~0UL,      { 0x0000, 0x0000, 0x0000},
- 	}
- };
-@@ -195,6 +191,7 @@ static const struct dw_hdmi_phy_config r
- 	{ 74250000,  0x8009, 0x0004, 0x0272},
- 	{ 148500000, 0x802b, 0x0004, 0x028d},
- 	{ 297000000, 0x8039, 0x0005, 0x028d},
-+	{ 594000000, 0x8039, 0x0000, 0x019d},
- 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
- };
- 
-@@ -240,26 +237,6 @@ static int rockchip_hdmi_parse_dt(struct
- 	return 0;
- }
- 
--static enum drm_mode_status
--dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
--			    const struct drm_display_info *info,
--			    const struct drm_display_mode *mode)
--{
--	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
--	int pclk = mode->clock * 1000;
--	bool valid = false;
--	int i;
--
--	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
--		if (pclk == mpll_cfg[i].mpixelclock) {
--			valid = true;
--			break;
--		}
--	}
--
--	return (valid) ? MODE_OK : MODE_BAD;
--}
--
- static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
- {
- }
-@@ -425,7 +402,6 @@ static struct rockchip_hdmi_chip_data rk
- };
- 
- static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
--	.mode_valid = dw_hdmi_rockchip_mode_valid,
- 	.mpll_cfg = rockchip_mpll_cfg,
- 	.cur_ctr = rockchip_cur_ctr,
- 	.phy_config = rockchip_phy_config,
-@@ -442,7 +418,6 @@ static struct rockchip_hdmi_chip_data rk
- };
- 
- static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
--	.mode_valid = dw_hdmi_rockchip_mode_valid,
- 	.mpll_cfg   = rockchip_mpll_cfg,
- 	.cur_ctr    = rockchip_cur_ctr,
- 	.phy_config = rockchip_phy_config,
-@@ -462,7 +437,6 @@ static struct rockchip_hdmi_chip_data rk
- };
- 
- static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
--	.mode_valid = dw_hdmi_rockchip_mode_valid,
- 	.mpll_cfg = rockchip_mpll_cfg,
- 	.cur_ctr = rockchip_cur_ctr,
- 	.phy_config = rockchip_phy_config,
-@@ -480,7 +454,6 @@ static struct rockchip_hdmi_chip_data rk
- };
- 
- static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
--	.mode_valid = dw_hdmi_rockchip_mode_valid,
- 	.mpll_cfg   = rockchip_mpll_cfg,
- 	.cur_ctr    = rockchip_cur_ctr,
- 	.phy_config = rockchip_phy_config,
-@@ -493,7 +466,6 @@ static struct rockchip_hdmi_chip_data rk
- };
- 
- static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
--	.mode_valid = dw_hdmi_rockchip_mode_valid,
- 	.mpll_cfg   = rockchip_mpll_cfg,
- 	.cur_ctr    = rockchip_cur_ctr,
- 	.phy_config = rockchip_phy_config,
-@@ -598,6 +570,14 @@ static int dw_hdmi_rockchip_bind(struct
- 	}
- 
- 	if (hdmi->chip_data == &rk3568_chip_data) {
-+		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
-+			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
-+					   RK3568_HDMI_SCLIN_MSK,
-+					   RK3568_HDMI_SDAIN_MSK |
-+					   RK3568_HDMI_SCLIN_MSK));
-+	}
-+
-+	if (hdmi->chip_data == &rk3568_chip_data) {
- 		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
- 			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
- 					   RK3568_HDMI_SCLIN_MSK,

patches-6.6/005-friendlyelec-nanopi-series.patch

@@ -16,7 +16,7 @@ Subject: [PATCH] friendlyelec-nanopi-series
 
 --- a/drivers/soc/Kconfig
 +++ b/drivers/soc/Kconfig
-@@ -27,5 +27,6 @@ source "drivers/soc/ti/Kconfig"
+@@ -31,5 +31,6 @@ source "drivers/soc/ti/Kconfig"
  source "drivers/soc/ux500/Kconfig"
  source "drivers/soc/versatile/Kconfig"
  source "drivers/soc/xilinx/Kconfig"
@@ -25,7 +25,7 @@ Subject: [PATCH] friendlyelec-nanopi-series
  endmenu
 --- a/drivers/soc/Makefile
 +++ b/drivers/soc/Makefile
-@@ -33,3 +33,4 @@ obj-y				+= ti/
+@@ -35,3 +35,4 @@ obj-y				+= ti/
  obj-$(CONFIG_ARCH_U8500)	+= ux500/
  obj-$(CONFIG_PLAT_VERSATILE)	+= versatile/
  obj-y				+= xilinx/

patches-6.6/007-rockchip-p3phy-fw.patch

@@ -17,7 +17,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
 
 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
 +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
-@@ -20,6 +20,7 @@
+@@ -21,6 +21,7 @@
  
  /* Register for RK3568 */
  #define GRF_PCIE30PHY_CON1			0x4
@@ -25,7 +25,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  #define GRF_PCIE30PHY_CON6			0x18
  #define GRF_PCIE30PHY_CON9			0x24
  #define GRF_PCIE30PHY_DA_OCM			(BIT(15) | BIT(31))
-@@ -63,6 +64,10 @@ struct rockchip_p3phy_ops {
+@@ -64,6 +65,10 @@ struct rockchip_p3phy_ops {
  	int (*phy_init)(struct rockchip_p3phy_priv *priv);
  };
  
@@ -36,7 +36,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
  {
  	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
-@@ -87,13 +92,14 @@ static int rockchip_p3phy_rk3568_init(st
+@@ -88,13 +93,14 @@ static int rockchip_p3phy_rk3568_init(st
  {
  	struct phy *phy = priv->phy;
  	bool bifurcation = false;
@@ -52,7 +52,7 @@ Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
  		dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
  		if (priv->lanes[i] > 1)
  			bifurcation = true;
-@@ -112,16 +118,35 @@ static int rockchip_p3phy_rk3568_init(st
+@@ -113,16 +119,35 @@ static int rockchip_p3phy_rk3568_init(st
  			     GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
  	}
  

patches-6.6/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch

@@ -4,7 +4,7 @@
  		power-domains = <&power RK3568_PD_PIPE>;
  		resets = <&cru SRST_USB3OTG0>;
  		snps,dis_u2_susphy_quirk;
-+                snps,xhci-trb-ent-quirk;
++		snps,xhci-trb-ent-quirk;
  		status = "disabled";
  	};
  
@@ -12,13 +12,13 @@
  		power-domains = <&power RK3568_PD_PIPE>;
  		resets = <&cru SRST_USB3OTG1>;
  		snps,dis_u2_susphy_quirk;
-+                snps,xhci-trb-ent-quirk;
++		snps,xhci-trb-ent-quirk;
  		status = "disabled";
  	};
  
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -1654,6 +1654,8 @@ static void dwc3_get_properties(struct d
+@@ -1609,6 +1609,8 @@ static void dwc3_get_properties(struct d
  				"snps,dis-del-phy-power-chg-quirk");
  	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
  				"snps,dis-tx-ipgap-linecheck-quirk");
@@ -26,30 +26,30 @@
 +				"snps,xhci-trb-ent-quirk");
  	dwc->resume_hs_terminations = device_property_read_bool(dev,
  				"snps,resume-hs-terminations");
- 	dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
+ 	dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
 --- a/drivers/usb/dwc3/core.h
 +++ b/drivers/usb/dwc3/core.h
-@@ -1104,6 +1104,9 @@ struct dwc3_scratchpad_array {
+@@ -1107,6 +1107,9 @@ struct dwc3_scratchpad_array {
   *			change quirk.
   * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
   *			check during HS transmit.
 + * @xhci_trb_ent_quirk: set if need to enable the Evaluate Next TRB(ENT)
-+ *			flag in the TRB data structure to force xHC to
++ * 		flag in the TRB data structure to force xHC to
 + *			pre-fetch the next TRB of a TD.
-  * @resume-hs-terminations: Set if we enable quirk for fixing improper crc
+  * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
   *			generation after resume from suspend.
-  * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
+  * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
-@@ -1327,6 +1330,7 @@ struct dwc3 {
+@@ -1331,6 +1334,7 @@ struct dwc3 {
  	unsigned		dis_u2_freeclk_exists_quirk:1;
  	unsigned		dis_del_phy_power_chg_quirk:1;
  	unsigned		dis_tx_ipgap_linecheck_quirk:1;
 +	unsigned		xhci_trb_ent_quirk:1;
  	unsigned		resume_hs_terminations:1;
+ 	unsigned		ulpi_ext_vbus_drv:1;
  	unsigned		parkmode_disable_ss_quirk:1;
- 	unsigned		gfladj_refclk_lpm_sel:1;
 --- a/drivers/usb/dwc3/host.c
 +++ b/drivers/usb/dwc3/host.c
-@@ -66,7 +66,7 @@ out:
+@@ -61,7 +61,7 @@ out:
  
  int dwc3_host_init(struct dwc3 *dwc)
  {
@@ -58,7 +58,7 @@
  	struct platform_device	*xhci;
  	int			ret, irq;
  	int			prop_idx = 0;
-@@ -97,6 +97,9 @@ int dwc3_host_init(struct dwc3 *dwc)
+@@ -92,6 +92,9 @@ int dwc3_host_init(struct dwc3 *dwc)
  	if (dwc->usb3_lpm_capable)
  		props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");
  
@@ -70,7 +70,7 @@
  
 --- a/drivers/usb/host/xhci-plat.c
 +++ b/drivers/usb/host/xhci-plat.c
-@@ -301,6 +301,9 @@ static int xhci_plat_probe(struct platfo
+@@ -250,6 +250,9 @@ int xhci_plat_probe(struct platform_devi
  		if (device_property_read_bool(tmpdev, "quirk-broken-port-ped"))
  			xhci->quirks |= XHCI_BROKEN_PORT_PED;
  
@@ -82,7 +82,7 @@
  	}
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3533,6 +3533,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3549,6 +3549,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	bool more_trbs_coming = true;
  	bool need_zero_pkt = false;
  	bool first_trb = true;
@@ -90,7 +90,7 @@
  	unsigned int num_trbs;
  	unsigned int start_cycle, num_sgs = 0;
  	unsigned int enqd_len, block_len, trb_buff_len, full_len;
-@@ -3569,6 +3570,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3585,6 +3586,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
  		need_zero_pkt = true;
  
@@ -104,7 +104,7 @@
  	td = &urb_priv->td[0];
  
  	/*
-@@ -3597,6 +3605,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3613,6 +3621,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  			first_trb = false;
  			if (start_cycle == 0)
  				field |= TRB_CYCLE;
@@ -118,7 +118,7 @@
  		} else
  			field |= ring->cycle_state;
  
-@@ -3605,6 +3620,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3621,6 +3636,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
  		 */
  		if (enqd_len + trb_buff_len < full_len) {
  			field |= TRB_CHAIN;
@@ -129,7 +129,7 @@
  						  &trb_buff_len,
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1525,7 +1525,11 @@ static inline const char *xhci_trb_type_
+@@ -1528,7 +1528,11 @@ static inline const char *xhci_trb_type_
  #define TRB_SEGMENT_SIZE	(TRBS_PER_SEGMENT*16)
  #define TRB_SEGMENT_SHIFT	(ilog2(TRB_SEGMENT_SIZE))
  /* TRB buffer pointers can't cross 64KB boundaries */
@@ -141,7 +141,7 @@
  #define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
  /* How much data is left before the 64KB boundary? */
  #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
-@@ -1843,6 +1847,7 @@ struct xhci_hcd {
+@@ -1848,6 +1852,7 @@ struct xhci_hcd {
  #define XHCI_STATE_HALTED	(1 << 1)
  #define XHCI_STATE_REMOVING	(1 << 2)
  	unsigned long long	quirks;

patches-6.6/013-rk3399-add-dwc3-xhci-usb-trb-quirk.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -459,6 +459,7 @@
+@@ -486,6 +486,7 @@
  			snps,dis_enblslpm_quirk;
  			snps,dis-u2-freeclk-exists-quirk;
  			snps,dis_u2_susphy_quirk;
@@ -8,7 +8,7 @@
  			snps,dis-del-phy-power-chg-quirk;
  			snps,dis-tx-ipgap-linecheck-quirk;
  			power-domains = <&power RK3399_PD_USB3>;
-@@ -495,6 +496,7 @@
+@@ -522,6 +523,7 @@
  			snps,dis_enblslpm_quirk;
  			snps,dis-u2-freeclk-exists-quirk;
  			snps,dis_u2_susphy_quirk;

patches-6.6/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch

@@ -9,7 +9,7 @@ Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
 
 --- a/drivers/net/phy/realtek.c
 +++ b/drivers/net/phy/realtek.c
-@@ -27,6 +27,8 @@
+@@ -28,6 +28,8 @@
  #define RTL821x_EXT_PAGE_SELECT			0x1e
  #define RTL821x_PAGE_SELECT			0x1f
  
@@ -18,7 +18,7 @@ Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
  #define RTL8211F_PHYCR1				0x18
  #define RTL8211F_PHYCR2				0x19
  #define RTL8211F_INSR				0x1d
-@@ -349,6 +351,7 @@ static int rtl8211f_config_init(struct p
+@@ -356,6 +358,7 @@ static int rtl8211f_config_init(struct p
  	struct rtl821x_priv *priv = phydev->priv;
  	struct device *dev = &phydev->mdio.dev;
  	u16 val_txdly, val_rxdly;
@@ -26,7 +26,7 @@ Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
  	int ret;
  
  	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
-@@ -425,6 +428,15 @@ static int rtl8211f_config_init(struct p
+@@ -432,6 +435,15 @@ static int rtl8211f_config_init(struct p
  		}
  	}
  

patches-6.6/107-mmc-core-set-initial-signal-voltage-on-power-off.patch

@@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
 
 --- a/drivers/mmc/core/core.c
 +++ b/drivers/mmc/core/core.c
-@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host
+@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host
  
  	mmc_pwrseq_power_off(host);
  

patches-6.6/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch

@@ -1,6 +1,6 @@
 --- a/arch/arm64/Kconfig
 +++ b/arch/arm64/Kconfig
-@@ -1165,6 +1165,14 @@ config SOCIONEXT_SYNQUACER_PREITS
+@@ -1229,6 +1229,14 @@ config SOCIONEXT_SYNQUACER_PREITS
  
  	  If unsure, say Y.
  
@@ -83,7 +83,7 @@
  	};
  
  	usb_host0_ehci: usb@fd800000 {
-@@ -978,7 +985,7 @@
+@@ -990,7 +997,7 @@
  		num-ib-windows = <6>;
  		num-ob-windows = <2>;
  		max-link-speed = <2>;

patches-6.6/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch

@@ -9,19 +9,19 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 
 --- a/drivers/irqchip/irq-gic-v3-its.c
 +++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -45,6 +45,7 @@
+@@ -42,6 +42,7 @@
- 
+ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
- #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
+ #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
- #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
+ #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
-+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE	(1 << 2)
++#define ITS_FLAGS_FORCE_NO_LOCAL_CACHE		(1ULL << 2)
+ #define ITS_FLAGS_FORCE_NON_SHAREABLE		(1ULL << 3)
  
  #define RD_LOCAL_LPI_ENABLED                    BIT(0)
- #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
+@@ -2201,6 +2202,11 @@ static struct page *its_allocate_prop_ta
-@@ -2203,6 +2204,11 @@ static struct page *its_allocate_prop_ta
  {
  	struct page *prop_page;
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
 +		gfp_flags |= GFP_DMA;
 +	}
@@ -29,7 +29,7 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
  	if (!prop_page)
  		return NULL;
-@@ -2326,6 +2332,7 @@ static int its_setup_baser(struct its_no
+@@ -2324,6 +2330,7 @@ static int its_setup_baser(struct its_no
  	u32 alloc_pages, psz;
  	struct page *page;
  	void *base;
@@ -37,23 +37,23 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  
  	psz = baser->psz;
  	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
-@@ -2337,7 +2344,10 @@ static int its_setup_baser(struct its_no
+@@ -2335,7 +2342,10 @@ static int its_setup_baser(struct its_no
  		order = get_order(GITS_BASER_PAGES_MAX * psz);
  	}
  
 -	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
 +	gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		gfp_flags |= GFP_DMA;
 +	page = alloc_pages_node(its->numa_node, gfp_flags, order);
  	if (!page)
  		return -ENOMEM;
  
-@@ -2384,6 +2394,13 @@ retry_baser:
+@@ -2385,6 +2395,13 @@ retry_baser:
  	its_write_baser(its, baser, val);
  	tmp = baser->val;
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +		if (tmp & GITS_BASER_SHAREABILITY_MASK)
 +			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
 +		else
@@ -63,44 +63,44 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
  		/*
  		 * Shareability didn't stick. Just use
-@@ -2966,6 +2983,10 @@ static struct page *its_allocate_pending
+@@ -2971,6 +2988,10 @@ static struct page *its_allocate_pending
  {
  	struct page *pend_page;
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +		gfp_flags |= GFP_DMA;
 +	}
 +
  	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
  				get_order(LPI_PENDBASE_SZ));
  	if (!pend_page)
-@@ -3121,6 +3142,9 @@ static void its_cpu_init_lpis(void)
+@@ -3126,6 +3147,9 @@ static void its_cpu_init_lpis(void)
  	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
  	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
 +
- 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
- 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ 		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
- 			/*
+ 
-@@ -3145,6 +3169,9 @@ static void its_cpu_init_lpis(void)
+@@ -3153,6 +3177,9 @@ static void its_cpu_init_lpis(void)
  	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
  	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
 +
- 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
- 		/*
+ 		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
- 		 * The HW reports non-shareable, we must remove the
+ 
-@@ -3308,7 +3335,12 @@ static bool its_alloc_table_entry(struct
+@@ -3319,7 +3346,12 @@ static bool its_alloc_table_entry(struct
  
  	/* Allocate memory for 2nd level table */
  	if (!table[idx]) {
 -		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
 +		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
++		if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +			gfp_flags |= GFP_DMA;
 +		}
 +
@@ -108,7 +108,7 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  					get_order(baser->psz));
  		if (!page)
  			return false;
-@@ -3397,6 +3429,7 @@ static struct its_device *its_create_dev
+@@ -3408,6 +3440,7 @@ static struct its_device *its_create_dev
  	int nr_lpis;
  	int nr_ites;
  	int sz;
@@ -116,20 +116,20 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  
  	if (!its_alloc_device_table(its, dev_id))
  		return NULL;
-@@ -3404,7 +3437,11 @@ static struct its_device *its_create_dev
+@@ -3415,7 +3448,11 @@ static struct its_device *its_create_dev
  	if (WARN_ON(!is_power_of_2(nvecs)))
  		nvecs = roundup_pow_of_two(nvecs);
  
 -	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 +	gfp_flags = GFP_KERNEL;
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		gfp_flags |= GFP_DMA;
 +
 +	dev = kzalloc(sizeof(*dev), gfp_flags);
  	/*
  	 * Even if the device wants a single LPI, the ITT must be
  	 * sized as a power of two (and you need at least one bit...).
-@@ -3412,7 +3449,7 @@ static struct its_device *its_create_dev
+@@ -3423,7 +3460,7 @@ static struct its_device *its_create_dev
  	nr_ites = max(2, nvecs);
  	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
  	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
@@ -138,13 +138,13 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  	if (alloc_lpis) {
  		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
  		if (lpi_map)
-@@ -4727,6 +4764,13 @@ static bool __maybe_unused its_enable_qu
+@@ -4762,6 +4799,13 @@ static bool its_set_non_coherent(void *d
  	return true;
  }
  
 +static bool __maybe_unused its_enable_quirk_rk3568(void *data)
 +{
-+	gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
++	gic_rdists->flags |= ITS_FLAGS_FORCE_NO_LOCAL_CACHE;
 +
 +	return true;
 +}
@@ -152,8 +152,8 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  static const struct gic_quirk its_quirks[] = {
  #ifdef CONFIG_CAVIUM_ERRATUM_22375
  	{
-@@ -4773,6 +4817,14 @@ static const struct gic_quirk its_quirks
+@@ -4816,6 +4860,14 @@ static const struct gic_quirk its_quirks
- 		.init	= its_enable_quirk_hip07_161600802,
+ 		.init   = its_enable_rk3588001,
  	},
  #endif
 +#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
@@ -165,19 +165,19 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 +	},
 +#endif
  	{
- 	}
+ 		.desc   = "ITS: non-coherent attribute",
- };
+ 		.property = "dma-noncoherent",
-@@ -5028,6 +5080,7 @@ static int __init its_probe_one(struct r
+@@ -5077,6 +5129,7 @@ static int __init its_probe_one(struct i
  	struct page *page;
  	u32 ctlr;
  	int err;
 +	gfp_t gfp_flags;
  
- 	its_base = its_map_one(res, &err);
+ 	if (is_v4(its)) {
- 	if (!its_base)
+ 		if (!(its->typer & GITS_TYPER_VMOVP)) {
-@@ -5081,7 +5134,9 @@ static int __init its_probe_one(struct r
+@@ -5108,7 +5161,9 @@ static int __init its_probe_one(struct i
- 
+ 		}
- 	its->numa_node = numa_node;
+ 	}
  
 -	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
 +	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
@@ -186,13 +186,13 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
  				get_order(ITS_CMD_QUEUE_SZ));
  	if (!page) {
  		err = -ENOMEM;
-@@ -5112,6 +5167,9 @@ static int __init its_probe_one(struct r
+@@ -5134,6 +5189,9 @@ static int __init its_probe_one(struct i
  	gits_write_cbaser(baser, its->base + GITS_CBASER);
  	tmp = gits_read_cbaser(its->base + GITS_CBASER);
  
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
++	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
 +
- 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
- 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ 		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
- 			/*
+ 

patches-6.6/220-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch

@@ -16,7 +16,7 @@ Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 
 --- a/drivers/pci/pcie/Kconfig
 +++ b/drivers/pci/pcie/Kconfig
-@@ -110,6 +110,12 @@ config PCIEASPM_PERFORMANCE
+@@ -114,6 +114,12 @@ config PCIEASPM_PERFORMANCE
  	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
  endchoice
  
@@ -31,7 +31,7 @@ Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
  	depends on PCIEPORTBUS && PM
 --- a/drivers/pci/pcie/Makefile
 +++ b/drivers/pci/pcie/Makefile
-@@ -7,6 +7,7 @@ pcieportdrv-y			:= portdrv_core.o portdr
+@@ -7,6 +7,7 @@ pcieportdrv-y			:= portdrv.o rcec.o
  obj-$(CONFIG_PCIEPORTBUS)	+= pcieportdrv.o
  
  obj-$(CONFIG_PCIEASPM)		+= aspm.o

patches-6.6/411-arm64-dts-rockchip-rk3399-Enable-DFI.patch

@@ -14,7 +14,7 @@ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -1315,7 +1315,6 @@
+@@ -1362,7 +1362,6 @@
  		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
  		clocks = <&cru PCLK_DDR_MON>;
  		clock-names = "pclk_ddr_mon";

patches-6.6/412-arm64-dts-rockchip-rk356x-Add-DFI.patch

@@ -13,7 +13,7 @@ Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
 
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -956,6 +956,13 @@
+@@ -968,6 +968,13 @@
  		reg = <0x0 0xfe1a8100 0x0 0x20>;
  	};