config-6.12: enable ROCKCHIP DFI DEVFREQ event Driver

Signed-off-by: sbwml <admin@cooluc.com>
rockchip: add pwm-fan controller for nanopi r2s/r4s
2024-12-07 00:31:27 +08:00 · 2024-12-02 10:47:33 +08:00 · 2024-11-29 06:23:13 +08:00 · 2024-11-25 21:04:25 +08:00 · 2024-11-07 08:55:59 +08:00 · 2024-10-17 05:47:39 +08:00
41 changed files with 2419 additions and 418 deletions
--- a/3
+++ b/3
@ -7,7 +7,8 @@ BOARDNAME:=Rockchip
 FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
 SUBTARGETS:=armv8

-KERNEL_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.12
+KERNEL_TESTING_PATCHVER:=6.6

 define Target/Description
 	Build firmware image for Rockchip SoC devices.
--- a/armv8/base-files/etc/init.d/fa-fancontrol
+++ b/armv8/base-files/etc/init.d/fa-fancontrol
@ -1,7 +0,0 @@
-#!/bin/sh /etc/rc.common
-
-START=21
-start() {
-    /usr/bin/fa-fancontrol.sh &
-}
-
--- a/armv8/base-files/etc/rc.d/S21fa-fancontrol
+++ b/armv8/base-files/etc/rc.d/S21fa-fancontrol
@ -1 +0,0 @@
-../init.d/fa-fancontrol
--- a/armv8/base-files/usr/bin/cputemp.sh
+++ b/armv8/base-files/usr/bin/cputemp.sh
@ -1,14 +0,0 @@
-#!/bin/bash
-
-while true
-do
-echo "-----------------"
-echo "Curr freq: `cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq`,`cat /sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_cur_freq`"
-echo "Temp: `cat /sys/class/thermal/thermal_zone0/temp`"
-if [ -d /sys/devices/platform/pwm-fan ]; then
-    CUR=`cat /sys/devices/virtual/thermal/cooling_device0/cur_state`
-    MAX=`cat /sys/devices/virtual/thermal/cooling_device0/max_state`
-    echo "Fan Level: ${CUR}/${MAX}"
-fi
-sleep 5
-done
--- a/armv8/base-files/usr/bin/fa-fancontrol-direct.sh
+++ b/armv8/base-files/usr/bin/fa-fancontrol-direct.sh
@ -1,69 +0,0 @@
-#!/bin/bash
-
-# determine fan controller
-if [ -d /sys/devices/platform/pwm-fan ]; then
-    echo "pls use /usr/bin/fa-fancontrol.sh."
-    exit 1
-fi
-
-if [ ! -d /sys/class/pwm/pwmchip1 ]; then
-    echo "this model does not support pwm."
-    exit 1
-fi
-if [ ! -d /sys/class/pwm/pwmchip1/pwm0 ]; then
-    echo 0 > /sys/class/pwm/pwmchip1/export
-fi
-sleep 1
-while [ ! -d /sys/class/pwm/pwmchip1/pwm0 ];
-do
-    sleep 1
-done
-ISENABLE=`cat /sys/class/pwm/pwmchip1/pwm0/enable`
-if [ $ISENABLE -eq 1 ]; then
-    echo 0 > /sys/class/pwm/pwmchip1/pwm0/enable
-fi
-echo 50000 > /sys/class/pwm/pwmchip1/pwm0/period
-echo 1 > /sys/class/pwm/pwmchip1/pwm0/enable
-
-# max speed run 5s
-echo 46990 > /sys/class/pwm/pwmchip1/pwm0/duty_cycle
-sleep 5
-echo 25000 > /sys/class/pwm/pwmchip1/pwm0/duty_cycle
-
-# declare -a CpuTemps=(55000 43000 38000 32000)
-# declare -a PwmDutyCycles=(1000 20000 30000 45000)
-
-declare -a CpuTemps=(75000 63000 58000 52000)
-declare -a PwmDutyCycles=(25000 35000 45000 46990)
-
-declare -a Percents=(100 75 50 25)
-DefaultDuty=49990
-DefaultPercents=0
-
-while true
-do
-	temp=$(cat /sys/class/thermal/thermal_zone0/temp)
-	INDEX=0
-	FOUNDTEMP=0
-	DUTY=$DefaultDuty
-	PERCENT=$DefaultPercents
-	
-	for i in 0 1 2 3; do
-		if [ $temp -gt ${CpuTemps[$i]} ]; then
-			INDEX=$i
-			FOUNDTEMP=1
-			break
-		fi	
-	done
-	if [ ${FOUNDTEMP} == 1 ]; then
-		DUTY=${PwmDutyCycles[$i]}
-		PERCENT=${Percents[$i]}
-	fi
-
-	echo $DUTY > /sys/class/pwm/pwmchip1/pwm0/duty_cycle;
-
-        # echo "temp: $temp, duty: $DUTY, ${PERCENT}%"
-        # cat /sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_cur_freq
-
-	sleep 2s;
-done
--- a/armv8/base-files/usr/bin/fa-fancontrol.sh
+++ b/armv8/base-files/usr/bin/fa-fancontrol.sh
@ -1,36 +0,0 @@
-#!/bin/bash
-
-# determine fan controller
-if [ -d /sys/devices/platform/pwm-fan ]; then
-    (cd /sys/devices/virtual/thermal/thermal_zone0 && {        
-        logger -p user.info -t "pwmfan" "set the conditions for fan"
-        [ -f trip_point_3_temp ] && {
-            # select fan level 1
-            echo 50000 > trip_point_3_temp
-        }
-        [ -f trip_point_4_temp ] && {
-            # select fan level 2-4
-            echo 55000 > trip_point_4_temp
-        }
-    })
-
-    (cd /sys/devices/virtual/thermal/cooling_device0 && {
-        TYPE=`cat type`
-        if [ $TYPE = 'pwm-fan' ]; then
-            # run 5s
-            for i in `seq 1 5`; do
-                logger -p user.info -t "pwmfan" "start to spin ${i}/5"
-                echo 3 > cur_state
-                sleep 1
-            done
-            logger -p user.info -t "pwmfan" "set to auto"
-            echo 0 > cur_state
-        fi
-    })
-else
-    logger -p user.info -t "pwmfan" "not found cooling device"
-    if [ -d /sys/class/pwm/pwmchip1 ]; then
-        nohup /usr/bin/fa-fancontrol-direct.sh&
-    fi
-fi
-
--- a/armv8/config-6.12
+++ b/armv8/config-6.12
@ -0,0 +1,796 @@
+CONFIG_64BIT=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_3117295=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS=48
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_MHU_V2=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_RK3328_DMC_DEVFREQ=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SMMU=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CHARGER_GPIO=y
+CONFIG_CHARGER_RK817=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3576=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUGFS is not set
+# CONFIG_CMA_DEBUG is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMA=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTIG_ALLOC=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC64=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_POLYVAL=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SM3_NEON=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FHANDLE=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_SYSCON=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C=y
+# CONFIG_IIO_SCMI is not set
+CONFIG_IIO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_RK805_PWRKEY=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+# CONFIG_IR_GPIO_TX is not set
+# CONFIG_IR_IMON_DECODER is not set
+# CONFIG_IR_IMON_RAW is not set
+# CONFIG_IR_MCE_KBD_DECODER is not set
+# CONFIG_IR_PWM_TX is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_IR_RCMM_DECODER is not set
+# CONFIG_IR_SANYO_DECODER is not set
+# CONFIG_IR_SERIAL is not set
+# CONFIG_IR_SHARP_DECODER is not set
+# CONFIG_IR_SPI is not set
+# CONFIG_IR_TOY is not set
+# CONFIG_IR_XMP_DECODER is not set
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PWM_MULTICOLOR is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MAILBOX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK808=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NR_CPUS=256
+CONFIG_NR_LRU_GENS=7
+# CONFIG_NVHE_EL2_DEBUG is not set
+CONFIG_NVME_CORE=y
+CONFIG_NVME_HWMON=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
+CONFIG_NVMEM_SYSFS=y
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_NVMEM=y
+# CONFIG_OCTEON_EP is not set
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+CONFIG_OF=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEASPM_DEFAULT is not set
+CONFIG_PCIEASPM_EXT=y
+CONFIG_PCIEASPM_PERFORMANCE=y
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEASPM=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_STUB=y
+CONFIG_PCI=y
+CONFIG_PCS_XPCS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_DP=y
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL=y
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_OPP=y
+CONFIG_PM=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_ERRATUM_114514=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_VOP=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO=y
+CONFIG_SG_POOL=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THERMAL=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_TYPEC_ANX7411 is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+CONFIG_TYPEC=y
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VT=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
--- a/armv8/config-6.6
+++ b/armv8/config-6.6
@ -1,4 +1,5 @@
 CONFIG_64BIT=y
+CONFIG_ARC_EMAC_CORE=y
 CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
 CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
 CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
@ -19,17 +20,21 @@ CONFIG_ARCH_STACKWALK=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARCH_WANTS_NO_INSTR=y
 CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ARC_EMAC_CORE=y
-CONFIG_ARM64=y
 CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_BRBE=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1530923=y
 CONFIG_ARM64_ERRATUM_2051678=y
 CONFIG_ARM64_ERRATUM_2054223=y
 CONFIG_ARM64_ERRATUM_2067961=y
 CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
 CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_3117295=y
 CONFIG_ARM64_ERRATUM_819472=y
 CONFIG_ARM64_ERRATUM_824069=y
 CONFIG_ARM64_ERRATUM_826319=y
@ -39,35 +44,39 @@ CONFIG_ARM64_ERRATUM_843419=y
 CONFIG_ARM64_ERRATUM_858921=y
 CONFIG_ARM64_HW_AFDBM=y
 CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
 CONFIG_ARM64_PA_BITS=48
 CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PAGE_SHIFT=12
 CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_PTR_AUTH=y
 CONFIG_ARM64_RAS_EXTN=y
 CONFIG_ARM64_SME=y
 CONFIG_ARM64_SVE=y
 CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=48
 # CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS=48
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
 CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM64=y
 CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
 CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-CONFIG_ARM_GIC=y
+CONFIG_ARM_ARCH_TIMER=y
 CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
 CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_MHU=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC=y
 CONFIG_ARM_MHU_V2=y
-CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_MHU=y
 CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_CPUIDLE=y
 CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_RK3328_DMC_DEVFREQ=y
 # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
 CONFIG_ARM_SCMI_CPUFREQ=y
 CONFIG_ARM_SCMI_HAVE_SHMEM=y
@ -77,26 +86,26 @@ CONFIG_ARM_SCMI_POWER_DOMAIN=y
 CONFIG_ARM_SCMI_PROTOCOL=y
 # CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
 CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
-CONFIG_ARM_SCMI_TRANSPORT_SMC=y
 CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
 CONFIG_ARM_SCPI_CPUFREQ=y
 CONFIG_ARM_SCPI_POWER_DOMAIN=y
 CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
 # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
 # CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SMMU=y
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_GPIO=y
 CONFIG_BACKLIGHT_PWM=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
 CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG=y
 # CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NVME=y
 CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
@ -104,8 +113,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BLK_PM=y
 CONFIG_BRCMSTB_GISB_ARB=y
-CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BUFFER_HEAD=y
 CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
 CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
@ -113,8 +122,7 @@ CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
 CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
 CONFIG_CC_NO_ARRAY_BOUNDS=y
 CONFIG_CHARGER_GPIO=y
-# CONFIG_CHARGER_RK817 is not set
-CONFIG_CLKSRC_MMIO=y
+CONFIG_CHARGER_RK817=y
 CONFIG_CLK_PX30=y
 CONFIG_CLK_RK3308=y
 CONFIG_CLK_RK3328=y
@ -122,35 +130,35 @@ CONFIG_CLK_RK3368=y
 CONFIG_CLK_RK3399=y
 CONFIG_CLK_RK3568=y
 CONFIG_CLK_RK3588=y
+CONFIG_CLKSRC_MMIO=y
 CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
 CONFIG_CMA_ALIGNMENT=8
 CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
 # CONFIG_CMA_DEBUGFS is not set
+# CONFIG_CMA_DEBUG is not set
 CONFIG_CMA_SIZE_MBYTES=16
 # CONFIG_CMA_SIZE_SEL_MAX is not set
 CONFIG_CMA_SIZE_SEL_MBYTES=y
 # CONFIG_CMA_SIZE_SEL_MIN is not set
 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
 # CONFIG_CMA_SYSFS is not set
-CONFIG_COMMON_CLK=y
+CONFIG_CMA=y
 CONFIG_COMMON_CLK_RK808=y
 CONFIG_COMMON_CLK_ROCKCHIP=y
 CONFIG_COMMON_CLK_SCMI=y
 CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK=y
 CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CONFIGFS_FS=y
 CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
 CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTEXT_TRACKING=y
 CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUFREQ_DT=y
 CONFIG_CPU_FREQ_GOV_ATTR_SET=y
 # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
 # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
@ -159,9 +167,10 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 # CONFIG_CPU_FREQ_GOV_USERSPACE is not set
 CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
 CONFIG_CPU_IDLE_GOV_MENU=y
 CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_IDLE=y
 CONFIG_CPU_ISOLATION=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_PM=y
@ -172,19 +181,19 @@ CONFIG_CRASH_DUMP=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC64=y
 CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC64=y
 CONFIG_CRC_T10DIF=y
 CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
 CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64=y
 CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32=y
 CONFIG_CRYPTO_CRC64_ROCKSOFT=y
-CONFIG_CRYPTO_CRCT10DIF=y
 CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF=y
 CONFIG_CRYPTO_CRYPTD=y
 # CONFIG_CRYPTO_DEV_ROCKCHIP is not set
 CONFIG_CRYPTO_GHASH_ARM64_CE=y
@ -194,14 +203,14 @@ CONFIG_CRYPTO_LIB_GF128MUL=y
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_POLYVAL=y
 CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_POLYVAL=y
 CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SM3=y
 CONFIG_CRYPTO_SM3_NEON=y
-CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM3=y
 CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
 CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_SM4=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
@ -213,9 +222,9 @@ CONFIG_DEVFREQ_GOV_USERSPACE=y
 # CONFIG_DEVFREQ_THERMAL is not set
 CONFIG_DEVMEM=y
 # CONFIG_DEVPORT is not set
-CONFIG_DMADEVICES=y
 CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
 CONFIG_DMA_CMA=y
+CONFIG_DMADEVICES=y
 CONFIG_DMA_DIRECT_REMAP=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
@ -236,31 +245,29 @@ CONFIG_EMAC_ROCKCHIP=y
 CONFIG_ENERGY_MODEL=y
 CONFIG_EXCLUSIVE_SYSTEM_RAM=y
 CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXTCON=y
 CONFIG_F2FS_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
-# CONFIG_FORTIFY_SOURCE is not set
+CONFIG_FIXED_PHY=y
 CONFIG_FRAME_POINTER=y
 CONFIG_FS_IOMAP=y
 CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
 CONFIG_FUNCTION_ALIGNMENT=4
 CONFIG_FUNCTION_ALIGNMENT_4B=y
-CONFIG_FWNODE_MDIO=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_FW_LOADER_SYSFS=y
+CONFIG_FWNODE_MDIO=y
 CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_CPU_VULNERABILITIES=y
 CONFIG_GENERIC_CSUM=y
@ -271,8 +278,8 @@ CONFIG_GENERIC_IOREMAP=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
 CONFIG_GENERIC_MSI_IRQ=y
 CONFIG_GENERIC_PCI_IOMAP=y
@ -283,71 +290,71 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_CDEV=y
 CONFIG_GPIO_DWAPB=y
-CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_ROCKCHIP=y
 CONFIG_GPIO_SYSCON=y
 CONFIG_GRO_CELLS=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
 CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
+CONFIG_HAS_IOPORT=y
 CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HID=y
 CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CORE_SYNC=y
 CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
 # CONFIG_HOTPLUG_PCI_CPCI is not set
 CONFIG_HOTPLUG_PCI_PCIE=y
 CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HOTPLUG_PCI=y
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
 CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
+CONFIG_HWMON=y
 CONFIG_HW_RANDOM_ROCKCHIP_RK3568=y
-CONFIG_I2C=y
+CONFIG_HW_RANDOM=y
+CONFIG_HWSPINLOCK=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_COMPAT=y
 CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_RK3X=y
-CONFIG_IIO=y
+CONFIG_I2C=y
 # CONFIG_IIO_SCMI is not set
+CONFIG_IIO=y
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_INDIRECT_PIO=y
-CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_FF_MEMLESS=y
 CONFIG_INPUT_KEYBOARD=y
 CONFIG_INPUT_LEDS=y
 CONFIG_INPUT_MATRIXKMAP=y
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSE=y
 CONFIG_INPUT_RK805_PWRKEY=y
 CONFIG_INPUT_SPARSEKMAP=y
-# CONFIG_IOMMUFD is not set
+CONFIG_INPUT=y
 CONFIG_IOMMU_API=y
 # CONFIG_IOMMU_DEBUGFS is not set
 # CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
 # CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
 CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
 CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMUFD is not set
 # CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
 # CONFIG_IOMMU_IO_PGTABLE_DART is not set
-CONFIG_IOMMU_IO_PGTABLE_LPAE=y
 # CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+CONFIG_IOMMU_IO_PGTABLE=y
+CONFIG_IOMMU_IOVA=y
 CONFIG_IOMMU_SUPPORT=y
 # CONFIG_IO_STRICT_DEVMEM is not set
 # CONFIG_IR_GPIO_TX is not set
@ -355,6 +362,13 @@ CONFIG_IOMMU_SUPPORT=y
 # CONFIG_IR_IMON_RAW is not set
 # CONFIG_IR_MCE_KBD_DECODER is not set
 # CONFIG_IR_PWM_TX is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
 # CONFIG_IR_RCMM_DECODER is not set
 # CONFIG_IR_SANYO_DECODER is not set
 # CONFIG_IR_SERIAL is not set
@ -362,13 +376,6 @@ CONFIG_IOMMU_SUPPORT=y
 # CONFIG_IR_SPI is not set
 # CONFIG_IR_TOY is not set
 # CONFIG_IR_XMP_DECODER is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_TIME_ACCOUNTING=y
-CONFIG_IRQ_WORK=y
 CONFIG_JBD2=y
 CONFIG_JFFS2_ZLIB=y
 CONFIG_JUMP_LABEL=y
@ -377,14 +384,14 @@ CONFIG_KCMP=y
 CONFIG_KEXEC_CORE=y
 CONFIG_KEXEC_FILE=y
 CONFIG_KSM=y
-CONFIG_KVM=y
 CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
 CONFIG_KVM_MMIO=y
 CONFIG_KVM_VFIO=y
+CONFIG_KVM=y
 # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
 CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
 # CONFIG_LEDS_PWM_MULTICOLOR is not set
+CONFIG_LEDS_PWM=y
 CONFIG_LEDS_SYSCON=y
 CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_LEDS_TRIGGER_PANIC=y
@ -394,14 +401,14 @@ CONFIG_LOCALVERSION_AUTO=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_LOG_BUF_SHIFT=19
-CONFIG_MAGIC_SYSRQ=y
 CONFIG_MAGIC_SYSRQ_SERIAL=y
-CONFIG_MAILBOX=y
+CONFIG_MAGIC_SYSRQ=y
 # CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
+CONFIG_MAILBOX=y
 CONFIG_MDIO_BUS_MUX_GPIO=y
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
 CONFIG_MEMFD_CREATE=y
@ -413,11 +420,9 @@ CONFIG_MFD_RK8XX_I2C=y
 CONFIG_MFD_RK8XX_SPI=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK=y
 CONFIG_MMC_CQHCI=y
-CONFIG_MMC_DW=y
 # CONFIG_MMC_DW_BLUEFIELD is not set
 # CONFIG_MMC_DW_EXYNOS is not set
 # CONFIG_MMC_DW_HI3798CV200 is not set
@ -425,46 +430,48 @@ CONFIG_MMC_DW=y
 # CONFIG_MMC_DW_PCI is not set
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_MMC_SDHCI=y
+CONFIG_MMC_DW=y
 CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_OF_DWCMSHC=y
 # CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC=y
 CONFIG_MMU_LAZY_TLB_REFCOUNT=y
 CONFIG_MODULES_USE_ELF_RELA=y
 CONFIG_MOTORCOMM_PHY=y
 # CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
 CONFIG_MOUSE_PS2_BYD=y
 CONFIG_MOUSE_PS2_CYPRESS=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
 CONFIG_MOUSE_PS2_LOGIPS2PP=y
 CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
 CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 CONFIG_MOUSE_PS2_TRACKPOINT=y
+CONFIG_MOUSE_PS2=y
 # CONFIG_MOUSE_SERIAL is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 CONFIG_MQ_IOSCHED_DEADLINE=y
 # CONFIG_MTD_CFI is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_SPLIT_FIRMWARE=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_SG_DMA_FLAGS=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MT7530=y
 CONFIG_NET_DSA_MT7530_MDIO=y
 CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_MT7530=y
 CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_DSA=y
 CONFIG_NET_EGRESS=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_INGRESS=y
@ -472,24 +479,23 @@ CONFIG_NET_PTP_CLASSIFY=y
 CONFIG_NET_SELFTESTS=y
 CONFIG_NET_SWITCHDEV=y
 CONFIG_NET_XGRESS=y
-CONFIG_NLS=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_NOP_USB_XCEIV=y
+CONFIG_NLS=y
 CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_NR_CPUS=256
 CONFIG_NR_LRU_GENS=7
 # CONFIG_NVHE_EL2_DEBUG is not set
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-# CONFIG_NVMEM_ROCKCHIP_OTP is not set
-CONFIG_NVMEM_SYSFS=y
 CONFIG_NVME_CORE=y
 CONFIG_NVME_HWMON=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
+CONFIG_NVMEM_SYSFS=y
 # CONFIG_NVME_MULTIPATH is not set
+CONFIG_NVMEM=y
 # CONFIG_OCTEON_EP is not set
-CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_DYNAMIC=y
 CONFIG_OF_EARLY_FLATTREE=y
@ -501,6 +507,7 @@ CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
 CONFIG_OF_OVERLAY=y
 CONFIG_OF_RESOLVE=y
+CONFIG_OF=y
 # CONFIG_OVERLAY_FS_XINO_AUTO is not set
 CONFIG_PADATA=y
 CONFIG_PAGE_POOL=y
@ -511,38 +518,37 @@ CONFIG_PANIC_ON_OOPS_VALUE=0
 CONFIG_PANIC_TIMEOUT=0
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DOMAINS=y
 CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
 # CONFIG_PCIEASPM_DEFAULT is not set
 CONFIG_PCIEASPM_EXT=y
 CONFIG_PCIEASPM_PERFORMANCE=y
 # CONFIG_PCIEASPM_POWERSAVE is not set
 # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
+CONFIG_PCIEASPM=y
+CONFIG_PCI_ECAM=y
 CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_DW=y
 CONFIG_PCIE_PME=y
-CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIEPORTBUS=y
 CONFIG_PCIE_ROCKCHIP_DW_HOST=y
 CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
+CONFIG_PCIE_ROCKCHIP=y
 CONFIG_PCI_HOST_COMMON=y
 CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_MSI=y
 CONFIG_PCI_STUB=y
+CONFIG_PCI=y
 CONFIG_PCS_XPCS=y
 CONFIG_PER_VMA_LOCK=y
 CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYLIB=y
 CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLIB=y
 CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_ROCKCHIP_DP=y
 # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_DP=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
 # CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
 # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
@ -553,44 +559,45 @@ CONFIG_PHY_ROCKCHIP_PCIE=y
 CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PHY_ROCKCHIP_USB=y
-CONFIG_PINCTRL=y
+CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PINCTRL_RK805=y
 CONFIG_PINCTRL_ROCKCHIP=y
 # CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL=y
 CONFIG_PL330_DMA=y
 CONFIG_PLATFORM_MHU=y
-CONFIG_PM=y
 CONFIG_PM_CLK=y
-CONFIG_PM_DEVFREQ=y
 # CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_DEVFREQ=y
 CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_GENERIC_DOMAINS=y
 CONFIG_PM_OPP=y
+CONFIG_PM=y
 CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
 CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_POWER_SUPPLY=y
 CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
 CONFIG_PREEMPT_BUILD=y
 CONFIG_PREEMPT_COUNT=y
+CONFIG_PREEMPTION=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT=y
 CONFIG_PRINTK_TIME=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
 CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
+CONFIG_PTP_1588_CLOCK=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SYSFS=y
+CONFIG_PWM=y
 # CONFIG_QFMT_V2 is not set
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
 CONFIG_QUOTACTL=y
+CONFIG_QUOTA=y
 CONFIG_RAID_ATTRS=y
 CONFIG_RANDOMIZE_BASE=y
 CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
@ -600,24 +607,25 @@ CONFIG_RATIONAL=y
 # CONFIG_RAVE_SP_CORE is not set
 CONFIG_RCU_TRACE=y
 CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
+CONFIG_REGMAP=y
 CONFIG_REGULATOR_ARM_SCMI=y
 CONFIG_REGULATOR_FAN53555=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR=y
 CONFIG_RELOCATABLE=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_SCMI=y
 CONFIG_RFS_ACCEL=y
 CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_ROCKCHIP_ERRATUM_114514=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
 CONFIG_ROCKCHIP_GRF=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ROCKCHIP_IOMMU=y
@ -627,8 +635,8 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y
 # CONFIG_ROCKCHIP_SARADC is not set
 CONFIG_ROCKCHIP_THERMAL=y
 CONFIG_ROCKCHIP_TIMER=y
-CONFIG_ROCKCHIP_VOP=y
 CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_VOP=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 CONFIG_RPS=y
 CONFIG_RSEQ=y
@ -640,62 +648,62 @@ CONFIG_RTC_NVMEM=y
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_SCHED_MC=y
-CONFIG_SCSI=y
 CONFIG_SCSI_COMMON=y
 # CONFIG_SCSI_LOWLEVEL is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_SCSI_SAS_ATTRS=y
 CONFIG_SCSI_SAS_HOST_SMP=y
 CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI=y
 # CONFIG_SECURITY_DMESG_RESTRICT is not set
 CONFIG_SENSORS_ARM_SCMI=y
 CONFIG_SENSORS_ARM_SCPI=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_EXAR=y
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
 CONFIG_SERIAL_MCTRL_GPIO=y
 CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
 CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO=y
 CONFIG_SG_POOL=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_SMP=y
 CONFIG_SOCK_RX_QUEUE_MAPPING=y
 CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM=y
 CONFIG_SPI_BITBANG=y
 CONFIG_SPI_DYNAMIC=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
-CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_SPI=y
 CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
 # CONFIG_SQUASHFS_EMBEDDED is not set
 CONFIG_SQUASHFS_FILE_CACHE=y
 # CONFIG_SQUASHFS_FILE_DIRECT is not set
 CONFIG_SRAM=y
-CONFIG_STACKPROTECTOR=y
 CONFIG_STACKPROTECTOR_PER_TASK=y
 CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKPROTECTOR=y
 CONFIG_STACKTRACE=y
 CONFIG_STMMAC_ETH=y
 CONFIG_STMMAC_PLATFORM=y
@ -708,7 +716,6 @@ CONFIG_SYNC_FILE=y
 CONFIG_SYSCTL_EXCEPTION_TRACE=y
 CONFIG_SYSFS_SYSCALL=y
 # CONFIG_TEXTSEARCH is not set
-CONFIG_THERMAL=y
 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
 CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
 CONFIG_THERMAL_EMULATION=y
@ -716,19 +723,19 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_THERMAL_GOV_STEP_WISE=y
 CONFIG_THERMAL_HWMON=y
 CONFIG_THERMAL_OF=y
+CONFIG_THERMAL=y
 CONFIG_THREAD_INFO_IN_TASK=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
 CONFIG_TRACE_CLOCK=y
 CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
 # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_TRANS_TABLE=y
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
-CONFIG_TYPEC=y
 # CONFIG_TYPEC_ANX7411 is not set
 CONFIG_TYPEC_FUSB302=y
 # CONFIG_TYPEC_HD3SS3220 is not set
@ -742,43 +749,44 @@ CONFIG_TYPEC_FUSB302=y
 CONFIG_TYPEC_TCPM=y
 # CONFIG_TYPEC_TPS6598X is not set
 # CONFIG_TYPEC_WUSB3801 is not set
+CONFIG_TYPEC=y
 # CONFIG_UCLAMP_TASK is not set
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_UNINLINE_SPIN_UNLOCK=y
 CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
 CONFIG_USB_COMMON=y
-CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_HOST=y
 CONFIG_USB_DWC3_OF_SIMPLE=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_DWC3=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_PHY=y
 CONFIG_USB_ROLE_SWITCH=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI=y
 CONFIG_USB_ULPI_BUS=y
 CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB=y
 # CONFIG_VIRTIO_MENU is not set
 CONFIG_VIRTUALIZATION=y
 CONFIG_VMAP_STACK=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VT=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_XARRAY_MULTI=y
 CONFIG_XPS=y
 CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_BCJ=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
--- a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi
+++ b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-common.dtsi
@ -518,6 +518,9 @@
 };

 &rng {
+	rockchip,sample-count = <1000>;
+	quality = <900>;
+
 	status = "okay";
 };

--- a/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/files/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@ -14,24 +14,12 @@

 	fan: pwm-fan {
 		compatible = "pwm-fan";
-		cooling-levels = <0 18 102 170 255>;
+		cooling-levels = <0 18 60 100 255>;
 		#cooling-cells = <2>;
 		fan-supply = <&vcc5v0_sysp>;
 		pwms = <&pwm0 0 50000 0>;
 	};

-	gpio-key {
-		compatible = "gpio-key";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key1_pin>;
-
-		button@1 {
-			debounce-interval = <50>;
-			gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
-			wakeup-source;
-		};
-	};
-
 	gpio-leds {
 		compatible = "gpio-leds";

--- a/patches-6.12/001-gpio-sysfs-build.patch
+++ b/patches-6.12/001-gpio-sysfs-build.patch
@ -0,0 +1,11 @@
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -59,7 +59,7 @@ config DEBUG_GPIO
+ 	  that are most common when setting up new platforms or boards.
+ 
+ config GPIO_SYSFS
+-	bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
+	bool "/sys/class/gpio/... (sysfs interface)"
+ 	depends on SYSFS
+ 	select GPIO_CDEV # We need to encourage the new ABI
+ 	help
--- a/patches-6.12/007-rockchip-p3phy-fw.patch
+++ b/patches-6.12/007-rockchip-p3phy-fw.patch
@ -0,0 +1,92 @@
+From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Mon, 11 Jul 2022 20:35:52 +0800
+Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
+
+This fw fix some RX issue:
+1. connect detect error;
+2. transfer error in ssd huge data write(more than 10GB).
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
+---
+ drivers/phy/phy-rockchip-snps-pcie3.c  |   36 +-
+ drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
+ 2 files changed, 8225 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
+
+--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+@@ -21,6 +21,7 @@
+ 
+ /* Register for RK3568 */
+ #define GRF_PCIE30PHY_CON1			0x4
+#define GRF_PCIE30PHY_CON4			0x10
+ #define GRF_PCIE30PHY_CON6			0x18
+ #define GRF_PCIE30PHY_CON9			0x24
+ #define GRF_PCIE30PHY_DA_OCM			(BIT(15) | BIT(31))
+@@ -73,6 +74,10 @@ struct rockchip_p3phy_ops {
+ 	int (*phy_init)(struct rockchip_p3phy_priv *priv);
+ };
+ 
+static u16 phy_fw[] = {
+	#include "p3phy.fw"
+};
+
+ static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+ {
+ 	struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
+@@ -97,13 +102,14 @@ static int rockchip_p3phy_rk3568_init(st
+ {
+ 	struct phy *phy = priv->phy;
+ 	bool bifurcation = false;
+	int i;
+ 	int ret;
+ 	u32 reg;
+ 
+ 	/* Deassert PCIe PMA output clamp mode */
+ 	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
+ 
+-	for (int i = 0; i < priv->num_lanes; i++) {
+	for (i = 0; i < priv->num_lanes; i++) {
+ 		dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
+ 		if (priv->lanes[i] > 1)
+ 			bifurcation = true;
+@@ -122,16 +128,35 @@ static int rockchip_p3phy_rk3568_init(st
+ 			     GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
+ 	}
+ 
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
+
+ 	reset_control_deassert(priv->p30phy);
+ 
+ 	ret = regmap_read_poll_timeout(priv->phy_grf,
+ 				       GRF_PCIE30PHY_STATUS0,
+ 				       reg, SRAM_INIT_DONE(reg),
+ 				       0, 500);
+-	if (ret)
+	if (ret) {
+ 		dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
+ 		       __func__, reg);
+-	return ret;
+		return ret;
+	}
+
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+		     (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
+	for (i = 0; i < 8192; i++)
+		writel(phy_fw[i], priv->mmio + (i<<2));
+
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+		     (0x0 << 8) | (0x3 << (8 + 16)));
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+
+	dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
+	return 0;
+ }
+ 
+ static const struct rockchip_p3phy_ops rk3568_ops = {
--- a/patches-6.12/008-r4s-add-eeprom.patch
+++ b/patches-6.12/008-r4s-add-eeprom.patch
@ -0,0 +1,18 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -68,6 +68,15 @@
+ 	status = "disabled";
+ };
+ 
+&i2c2 {
+	eeprom@51 {
+		compatible = "microchip,24c02", "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+		read-only; /* This holds our MAC */
+	};
+};
+
+ &i2c4 {
+ 	status = "disabled";
+ };
--- a/patches-6.12/009-r4s-add-led-action-for-openwrt.patch
+++ b/patches-6.12/009-r4s-add-led-action-for-openwrt.patch
@ -0,0 +1,16 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -19,6 +19,13 @@
+ 	model = "FriendlyElec NanoPi R4S";
+ 	compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+ 
+	aliases {
+		led-boot = &sys_led;
+		led-failsafe = &sys_led;
+		led-running = &sys_led;
+		led-upgrade = &sys_led;
+	};
+
+ 	/delete-node/ display-subsystem;
+ 
+ 	gpio-leds {
--- a/patches-6.12/010-r4s-sd-signalling.patch
+++ b/patches-6.12/010-r4s-sd-signalling.patch
@ -0,0 +1,14 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -128,6 +128,11 @@
+ 	status = "disabled";
+ };
+ 
+&sdmmc {
+	/delete-property/ sd-uhs-sdr104;
+	cap-sd-highspeed;
+};
+
+ &u2phy0_host {
+ 	phy-supply = <&vdd_5v>;
+ };
--- a/patches-6.12/011-r4s-add-OF-node-for-pcie-eth.patch
+++ b/patches-6.12/011-r4s-add-OF-node-for-pcie-eth.patch
@ -0,0 +1,22 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -92,6 +92,19 @@
+ 	max-link-speed = <1>;
+ 	num-lanes = <1>;
+ 	vpcie3v3-supply = <&vcc3v3_sys>;
+
+	pcie@0 {
+		reg = <0x00000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@0,0 {
+			compatible = "pci10ec,8168";
+			reg = <0x000000 0 0 0 0>;
+
+			realtek,led-data = <0x870>;
+		};
+	};
+ };
+ 
+ &pinctrl {
--- a/patches-6.12/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch
+++ b/patches-6.12/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch
@ -0,0 +1,142 @@
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -333,6 +333,7 @@
+ 		power-domains = <&power RK3568_PD_PIPE>;
+ 		resets = <&cru SRST_USB3OTG0>;
+ 		snps,dis_u2_susphy_quirk;
+		snps,xhci-trb-ent-quirk;
+ 		status = "disabled";
+ 	};
+ 
+@@ -351,6 +352,7 @@
+ 		power-domains = <&power RK3568_PD_PIPE>;
+ 		resets = <&cru SRST_USB3OTG1>;
+ 		snps,dis_u2_susphy_quirk;
+		snps,xhci-trb-ent-quirk;
+ 		status = "disabled";
+ 	};
+ 
+--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
+@@ -1775,6 +1775,8 @@ static void dwc3_get_properties(struct d
+ 				"snps,dis-del-phy-power-chg-quirk");
+ 	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
+ 				"snps,dis-tx-ipgap-linecheck-quirk");
+	dwc->xhci_trb_ent_quirk = device_property_read_bool(dev,
+				"snps,xhci-trb-ent-quirk");
+ 	dwc->resume_hs_terminations = device_property_read_bool(dev,
+ 				"snps,resume-hs-terminations");
+ 	dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
+--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
+@@ -1129,6 +1129,9 @@ struct dwc3_scratchpad_array {
+  *			change quirk.
+  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
+  *			check during HS transmit.
+ * @xhci_trb_ent_quirk: set if need to enable the Evaluate Next TRB(ENT)
+ * 		flag in the TRB data structure to force xHC to
+ *			pre-fetch the next TRB of a TD.
+  * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
+  *			generation after resume from suspend.
+  * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
+@@ -1368,6 +1371,7 @@ struct dwc3 {
+ 	unsigned		dis_u2_freeclk_exists_quirk:1;
+ 	unsigned		dis_del_phy_power_chg_quirk:1;
+ 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
+	unsigned		xhci_trb_ent_quirk:1;
+ 	unsigned		resume_hs_terminations:1;
+ 	unsigned		ulpi_ext_vbus_drv:1;
+ 	unsigned		parkmode_disable_ss_quirk:1;
+--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
+@@ -167,6 +167,9 @@ int dwc3_host_init(struct dwc3 *dwc)
+ 	if (dwc->usb3_lpm_capable)
+ 		props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");
+ 
+	if (dwc->xhci_trb_ent_quirk)
+		props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-trb-ent-quirk");
+
+ 	if (dwc->usb2_lpm_disable)
+ 		props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb2-lpm-disable");
+ 
+--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
+@@ -265,6 +265,9 @@ int xhci_plat_probe(struct platform_devi
+ 		if (device_property_read_bool(tmpdev, "xhci-skip-phy-init-quirk"))
+ 			xhci->quirks |= XHCI_SKIP_PHY_INIT;
+ 
+		if (device_property_read_bool(tmpdev, "xhci-trb-ent-quirk"))
+			xhci->quirks |= XHCI_TRB_ENT_QUIRK;
+
+ 		device_property_read_u32(tmpdev, "imod-interval-ns",
+ 					 &xhci->imod_interval);
+ 	}
+--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
+@@ -3555,6 +3555,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ 	bool more_trbs_coming = true;
+ 	bool need_zero_pkt = false;
+ 	bool first_trb = true;
+	bool en_trb_ent = true;
+ 	unsigned int num_trbs;
+ 	unsigned int start_cycle, num_sgs = 0;
+ 	unsigned int enqd_len, block_len, trb_buff_len, full_len;
+@@ -3591,6 +3592,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ 	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
+ 		need_zero_pkt = true;
+ 
+	/*
+	 * Don't enable the ENT flag in the TRB if
+	 * the EP support bulk streaming protocol.
+	 */
+	if (urb->stream_id)
+		en_trb_ent = false;
+
+ 	td = &urb_priv->td[0];
+ 
+ 	/*
+@@ -3619,6 +3627,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ 			first_trb = false;
+ 			if (start_cycle == 0)
+ 				field |= TRB_CYCLE;
+			/*
+			 * Don't enable the ENT flag in the TRB if the
+			 * transfer length of the first TRB isn't an
+			 * integer multiple of the EP maxpacket.
+			 */
+			if (trb_buff_len % usb_endpoint_maxp(&urb->ep->desc))
+				en_trb_ent = false;
+ 		} else
+ 			field |= ring->cycle_state;
+ 
+@@ -3627,6 +3642,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+ 		 */
+ 		if (enqd_len + trb_buff_len < full_len) {
+ 			field |= TRB_CHAIN;
+			if (xhci->quirks & XHCI_TRB_ENT_QUIRK && en_trb_ent)
+				field |= TRB_ENT;
+ 			if (trb_is_link(ring->enqueue + 1)) {
+ 				if (xhci_align_td(xhci, urb, enqd_len,
+ 						  &trb_buff_len,
+--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
+@@ -1246,7 +1246,11 @@ static inline const char *xhci_trb_type_
+ #define TRB_SEGMENT_SIZE	(TRBS_PER_SEGMENT*16)
+ #define TRB_SEGMENT_SHIFT	(ilog2(TRB_SEGMENT_SIZE))
+ /* TRB buffer pointers can't cross 64KB boundaries */
+#ifdef CONFIG_ARCH_ROCKCHIP
+#define TRB_MAX_BUFF_SHIFT		12
+#else
+ #define TRB_MAX_BUFF_SHIFT		16
+#endif
+ #define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
+ /* How much data is left before the 64KB boundary? */
+ #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
+@@ -1564,6 +1568,7 @@ struct xhci_hcd {
+ #define XHCI_STATE_HALTED	(1 << 1)
+ #define XHCI_STATE_REMOVING	(1 << 2)
+ 	unsigned long long	quirks;
+#define XHCI_TRB_ENT_QUIRK	BIT_ULL(63)
+ #define	XHCI_LINK_TRB_QUIRK	BIT_ULL(0)
+ #define XHCI_RESET_EP_QUIRK	BIT_ULL(1) /* Deprecated */
+ #define XHCI_NEC_HOST		BIT_ULL(2)
--- a/patches-6.12/013-rk3399-add-dwc3-xhci-usb-trb-quirk.patch
+++ b/patches-6.12/013-rk3399-add-dwc3-xhci-usb-trb-quirk.patch
@ -0,0 +1,18 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi
+@@ -556,6 +556,7 @@
+ 			snps,dis_enblslpm_quirk;
+ 			snps,dis-u2-freeclk-exists-quirk;
+ 			snps,dis_u2_susphy_quirk;
+			snps,xhci-trb-ent-quirk;
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
+ 			power-domains = <&power RK3399_PD_USB3>;
+@@ -592,6 +593,7 @@
+ 			snps,dis_enblslpm_quirk;
+ 			snps,dis-u2-freeclk-exists-quirk;
+ 			snps,dis_u2_susphy_quirk;
+			snps,xhci-trb-ent-quirk;
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
+ 			power-domains = <&power RK3399_PD_USB3>;
--- a/patches-6.12/014-rockchip-add-pwm-fan-controller-for-nanopi-r2s-r4s.patch
+++ b/patches-6.12/014-rockchip-add-pwm-fan-controller-for-nanopi-r2s-r4s.patch
@ -0,0 +1,45 @@
+From 508a0a0d4e2e7b547950b2adb15594a75654708f Mon Sep 17 00:00:00 2001
+From: sbwml <admin@cooluc.com>
+Date: Mon, 2 Dec 2024 10:34:33 +0800
+Subject: [PATCH] rockchip: add pwm-fan controller for nanopi r2s/r4s
+
+Signed-off-by: sbwml <admin@cooluc.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 8 ++++++++
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -115,6 +115,14 @@
+ 		regulator-boot-on;
+ 		vin-supply = <&vdd_5v>;
+ 	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 18 60 100 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vdd_5v>;
+		pwms = <&pwm2 0 50000 0>;
+	};
+ };
+ 
+ &cpu0 {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -69,6 +69,14 @@
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 18 60 100 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vdd_5v>;
+		pwms = <&pwm1 0 50000 0>;
+	};
+ };
+ 
+ &emmc_phy {
--- a/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch
+++ b/patches-6.12/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch
@ -0,0 +1,44 @@
+From edcc2833819f6750bf003b95a6ac856aced26276 Mon Sep 17 00:00:00 2001
+From: AnYun <amadeus@jmu.edu.cn>
+Date: Mon, 3 Apr 2023 23:26:04 +0800
+Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
+
+---
+ drivers/net/phy/realtek.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
+@@ -28,6 +28,8 @@
+ #define RTL821x_EXT_PAGE_SELECT			0x1e
+ #define RTL821x_PAGE_SELECT			0x1f
+ 
+#define RTL8211F_LCR				0x10
+#define RTL8211F_EEELCR				0x11
+ #define RTL8211F_PHYCR1				0x18
+ #define RTL8211F_PHYCR2				0x19
+ #define RTL8211F_INSR				0x1d
+@@ -372,6 +374,7 @@ static int rtl8211f_config_init(struct p
+ 	struct rtl821x_priv *priv = phydev->priv;
+ 	struct device *dev = &phydev->mdio.dev;
+ 	u16 val_txdly, val_rxdly;
+	u32 led_data;
+ 	int ret;
+ 
+ 	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
+@@ -447,6 +450,15 @@ static int rtl8211f_config_init(struct p
+ 			return ret;
+ 		}
+ 
+	ret = of_property_read_u32(dev->of_node,
+				   "realtek,led-data", &led_data);
+	if (!ret) {
+		phy_write(phydev, RTL821x_PAGE_SELECT, 0xd04);
+		phy_write(phydev, RTL8211F_LCR, led_data);
+		phy_write(phydev, RTL8211F_EEELCR, 0x0);
+		phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
+	}
+
+ 		return genphy_soft_reset(phydev);
+ 	}
+ 
--- a/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
+++ b/patches-6.12/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
@ -0,0 +1,35 @@
+From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 20 Feb 2019 07:38:34 +0000
+Subject: [PATCH] mmc: core: set initial signal voltage on power off
+
+Some boards have SD card connectors where the power rail cannot be switched
+off by the driver. If the card has not been power cycled, it may still be
+using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
+will fail to boot from a UHS card that continue to use 1.8V signaling.
+
+Set initial signal voltage in mmc_power_off() to allow re-boot to function.
+
+This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
+same issue have been seen on some Rockchip RK3399 boards.
+
+I am sending this as a RFC because I have no insights into SD/MMC subsystem,
+this change fix a re-boot issue on my boards and does not break emmc/sdio.
+Is this an acceptable workaround? Any advice is appreciated.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/mmc/core/core.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
+@@ -1370,6 +1370,8 @@ void mmc_power_off(struct mmc_host *host
+ 
+ 	mmc_pwrseq_power_off(host);
+ 
+	mmc_set_initial_signal_voltage(host);
+
+ 	host->ios.clock = 0;
+ 	host->ios.vdd = 0;
+ 
--- a/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
+++ b/patches-6.12/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
@ -0,0 +1,94 @@
+--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
+@@ -1303,6 +1303,14 @@ config SOCIONEXT_SYNQUACER_PREITS
+ 
+ 	  If unsure, say Y.
+ 
+config ROCKCHIP_ERRATUM_114514
+	bool "Rockchip RK3568 force no_local_cache"
+	default y
+	help
+	  They consider this as a SoC implement design instead of a bug.
+
+	  If unsure, say Y.
+
+ endmenu # "ARM errata workarounds via the alternatives framework"
+ 
+ choice
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -64,7 +64,7 @@
+ 		compatible = "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		bus-range = <0x0 0xf>;
+		bus-range = <0x10 0x1f>;
+ 		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ 			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ 			 <&cru CLK_PCIE30X1_AUX_NDFT>;
+@@ -87,7 +87,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <3>;
+-		msi-map = <0x0 &gic 0x1000 0x1000>;
+		msi-map = <0x1000 &its 0x1000 0x1000>;
+ 		num-lanes = <1>;
+ 		phys = <&pcie30phy>;
+ 		phy-names = "pcie-phy";
+@@ -117,7 +117,7 @@
+ 		compatible = "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		bus-range = <0x0 0xf>;
+		bus-range = <0x20 0x2f>;
+ 		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ 			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ 			 <&cru CLK_PCIE30X2_AUX_NDFT>;
+@@ -140,7 +140,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <3>;
+-		msi-map = <0x0 &gic 0x2000 0x1000>;
+		msi-map = <0x2000 &its 0x2000 0x1000>;
+ 		num-lanes = <2>;
+ 		phys = <&pcie30phy>;
+ 		phy-names = "pcie-phy";
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -358,14 +358,21 @@
+ 
+ 	gic: interrupt-controller@fd400000 {
+ 		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+
+ 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+-		      <0x0 0xfd460000 0 0x80000>; /* GICR */
+		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
+ 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+-		interrupt-controller;
+-		#interrupt-cells = <3>;
+-		mbi-alias = <0x0 0xfd410000>;
+-		mbi-ranges = <296 24>;
+-		msi-controller;
+		its: interrupt-controller@fd440000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xfd440000 0x0 0x20000>;
+		};
+ 	};
+ 
+ 	usb_host0_ehci: usb@fd800000 {
+@@ -1040,7 +1047,7 @@
+ 		num-ib-windows = <6>;
+ 		num-ob-windows = <2>;
+ 		max-link-speed = <2>;
+-		msi-map = <0x0 &gic 0x0 0x1000>;
+		msi-map = <0x0 &its 0x0 0x1000>;
+ 		num-lanes = <1>;
+ 		phys = <&combphy2 PHY_TYPE_PCIE>;
+ 		phy-names = "pcie-phy";
--- a/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
+++ b/patches-6.12/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
@ -0,0 +1,161 @@
+From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Thu, 3 Jun 2021 11:36:35 -0400
+Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
+
+---
+ drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
+ 1 file changed, 65 insertions(+), 5 deletions(-)
+
+--- a/drivers/irqchip/irq-gic-common.h
+++ b/drivers/irqchip/irq-gic-common.h
+@@ -34,5 +34,6 @@ extern const struct msi_parent_ops gic_v
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING    (1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED     (1 << 1)
+ #define RDIST_FLAGS_FORCE_NON_SHAREABLE        (1 << 2)
+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE       (1 << 3)
+ 
+ #endif /* _IRQ_GIC_COMMON_H */
+--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -2181,6 +2181,11 @@ static struct page *its_allocate_prop_ta
+ {
+ 	struct page *prop_page;
+ 
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+		pr_debug("ITS ALLOCATE PROP WORKAROUND\n");
+		gfp_flags |= GFP_DMA;
+	}
+
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+ 		return NULL;
+@@ -2303,6 +2308,7 @@ static int its_setup_baser(struct its_no
+ 	u64 baser_phys, tmp;
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+	gfp_t gfp_flags;
+ 	void *base;
+ 
+ 	psz = baser->psz;
+@@ -2315,7 +2321,10 @@ static int its_setup_baser(struct its_no
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
+	gfp_flags = GFP_KERNEL | __GFP_ZERO;
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+		gfp_flags |= GFP_DMA;
+	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2955,6 +2964,10 @@ static struct page *its_allocate_pending
+ {
+ 	struct page *pend_page;
+ 
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+		gfp_flags |= GFP_DMA;
+	}
+
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3303,7 +3316,12 @@ static bool its_alloc_table_entry(struct
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
+		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+			gfp_flags |= GFP_DMA;
+		}
+
+		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3387,6 +3405,7 @@ static struct its_device *its_create_dev
+ 	unsigned long *lpi_map = NULL;
+ 	unsigned long flags;
+ 	u16 *col_map = NULL;
+	gfp_t gfp_flags;
+ 	void *itt;
+ 	int lpi_base;
+ 	int nr_lpis;
+@@ -3399,7 +3418,11 @@ static struct its_device *its_create_dev
+ 	if (WARN_ON(!is_power_of_2(nvecs)))
+ 		nvecs = roundup_pow_of_two(nvecs);
+ 
+-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	gfp_flags = GFP_KERNEL;
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
+		gfp_flags |= GFP_DMA;
+
+	dev = kzalloc(sizeof(*dev), gfp_flags);
+ 	/*
+ 	 * Even if the device wants a single LPI, the ITT must be
+ 	 * sized as a power of two (and you need at least one bit...).
+@@ -3407,7 +3430,7 @@ static struct its_device *its_create_dev
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
+	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -4759,6 +4782,21 @@ static bool __maybe_unused its_enable_qu
+ 	return true;
+ }
+ 
+static bool __maybe_unused its_enable_rk3568001(void *data)
+{
+	struct its_node *its = data;
+
+	if (!of_machine_is_compatible("rockchip,rk3566") &&
+	    !of_machine_is_compatible("rockchip,rk3568"))
+		return false;
+
+	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
+	gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE |
+			     RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
+
+	return true;
+}
+
+ static bool __maybe_unused its_enable_rk3588001(void *data)
+ {
+ 	struct its_node *its = data;
+@@ -4829,6 +4867,12 @@ static const struct gic_quirk its_quirks
+ #endif
+ #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
+ 	{
+		.desc   = "ITS: Rockchip erratum RK3568001",
+		.iidr   = 0x0201743b,
+		.mask   = 0xffffffff,
+		.init   = its_enable_rk3568001,
+	},
+	{
+ 		.desc   = "ITS: Rockchip erratum RK3588001",
+ 		.iidr   = 0x0201743b,
+ 		.mask   = 0xffffffff,
+@@ -5097,6 +5141,7 @@ static int __init its_probe_one(struct i
+ {
+ 	u64 baser, tmp;
+ 	struct page *page;
+	gfp_t gfp_flags;
+ 	u32 ctlr;
+ 	int err;
+ 
+@@ -5132,7 +5177,9 @@ static int __init its_probe_one(struct i
+ 		}
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
+
+	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
--- a/patches-6.12/220-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
+++ b/patches-6.12/220-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
@ -0,0 +1,402 @@
+From d591c3f6efef5f50fc970aeeedbf9e03b7bd5d21 Mon Sep 17 00:00:00 2001
+From: Jon Lin <jon.lin@rock-chips.com>
+Date: Fri, 17 Jun 2022 10:38:30 +0800
+Subject: [PATCH] PCI: Add ROCKCHIP PCIe ASPM interface
+
+Change-Id: I1156bd10e352145d745899067bf43afda92d5a30
+Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
+---
+ drivers/pci/pcie/Kconfig    |   6 +
+ drivers/pci/pcie/Makefile   |   1 +
+ drivers/pci/pcie/aspm_ext.c | 339 ++++++++++++++++++++++++++++++++++++
+ include/linux/aspm_ext.h    |  16 ++
+ 4 files changed, 362 insertions(+)
+ create mode 100644 drivers/pci/pcie/aspm_ext.c
+ create mode 100644 include/linux/aspm_ext.h
+
+--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
+@@ -123,6 +123,12 @@ config PCIEASPM_PERFORMANCE
+ 	  Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
+ endchoice
+ 
+config PCIEASPM_EXT
+	tristate "Extend ASPM function"
+	depends on PCIEASPM
+	help
+	  This enables the extensions APIs for ASPM control.
+
+ config PCIE_PME
+ 	def_bool y
+ 	depends on PCIEPORTBUS && PM
+--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
+@@ -7,6 +7,7 @@ pcieportdrv-y			:= portdrv.o rcec.o
+ obj-$(CONFIG_PCIEPORTBUS)	+= pcieportdrv.o
+ 
+ obj-y				+= aspm.o
+obj-$(CONFIG_PCIEASPM_EXT)	+= aspm_ext.o
+ obj-$(CONFIG_PCIEAER)		+= aer.o err.o
+ obj-$(CONFIG_PCIEAER_INJECT)	+= aer_inject.o
+ obj-$(CONFIG_PCIE_PME)		+= pme.o
+--- /dev/null
+++ b/drivers/pci/pcie/aspm_ext.c
+@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip PCIe Apis For WIFI
+ *
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/aspm_ext.h>
+#include <linux/errno.h>
+
+
+static u32 rockchip_pcie_pcie_access_cap(struct pci_dev *pdev, int cap, uint offset,
+					 bool is_ext, bool is_write, u32 writeval)
+{
+	int cap_ptr = 0;
+	u32 ret = -1;
+	u32 readval;
+
+	if (!(pdev)) {
+		pci_err(pdev, "%s: pdev is NULL\n", __func__);
+		return ret;
+	}
+
+	/* Find Capability offset */
+	if (is_ext) {
+		/* removing max EXT_CAP_ID check as
+		 * linux kernel definition's max value is not updated yet as per spec
+		 */
+		cap_ptr = pci_find_ext_capability(pdev, cap);
+
+	} else {
+		/* removing max PCI_CAP_ID_MAX check as
+		 * previous kernel versions dont have this definition
+		 */
+		cap_ptr = pci_find_capability(pdev, cap);
+	}
+
+	/* Return if capability with given ID not found */
+	if (cap_ptr == 0) {
+		pci_err(pdev, "%s: PCI Cap(0x%02x) not supported.\n",
+		       __func__, cap);
+		return -EINVAL;
+	}
+
+	if (is_write) {
+		pci_write_config_dword(pdev, (cap_ptr + offset), writeval);
+		ret = 0;
+
+	} else {
+		pci_read_config_dword(pdev, (cap_ptr + offset), &readval);
+		ret = readval;
+	}
+
+	return ret;
+}
+
+static bool rockchip_pcie_bus_aspm_enable_dev(char *device, struct pci_dev *dev, bool enable)
+{
+	u32 linkctrl_before;
+	u32 linkctrl_after = 0;
+	u8 linkctrl_asm;
+
+	linkctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
+							false, false, 0);
+	linkctrl_asm = (linkctrl_before & PCI_EXP_LNKCTL_ASPMC);
+
+	if (enable) {
+		if (linkctrl_asm == PCI_EXP_LNKCTL_ASPM_L1) {
+			pci_err(dev, "%s: %s already enabled  linkctrl: 0x%x\n",
+			       __func__, device, linkctrl_before);
+			return false;
+		}
+		/* Enable only L1 ASPM (bit 1) */
+		rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
+					      true, (linkctrl_before | PCI_EXP_LNKCTL_ASPM_L1));
+	} else {
+		if (linkctrl_asm == 0) {
+			pci_err(dev, "%s: %s already disabled linkctrl: 0x%x\n",
+			       __func__, device, linkctrl_before);
+			return false;
+		}
+		/* Disable complete ASPM (bit 1 and bit 0) */
+		rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL, false,
+					      true, (linkctrl_before & (~PCI_EXP_LNKCTL_ASPMC)));
+	}
+
+	linkctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_CAP_ID_EXP, PCI_EXP_LNKCTL,
+						       false, false, 0);
+	pci_err(dev, "%s: %s %s, linkctrl_before: 0x%x linkctrl_after: 0x%x\n",
+	       __func__, device, (enable ? "ENABLE " : "DISABLE"),
+		linkctrl_before, linkctrl_after);
+
+	return true;
+}
+
+bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
+{
+	bool ret;
+
+	if (enable) {
+		/* Enable only L1 ASPM first RC then EP */
+		ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
+		ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
+	} else {
+		/* Disable complete ASPM first EP then RC */
+		ret = rockchip_pcie_bus_aspm_enable_dev("EP", child, enable);
+		ret = rockchip_pcie_bus_aspm_enable_dev("RC", parent, enable);
+	}
+
+	return ret;
+}
+
+static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
+				    u32 clear, u32 set)
+{
+	u32 val;
+
+	pci_read_config_dword(pdev, pos, &val);
+	val &= ~clear;
+	val |= set;
+	pci_write_config_dword(pdev, pos, val);
+}
+
+/* Convert L1SS T_pwr encoding to usec */
+static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
+{
+	switch (scale) {
+	case 0:
+		return val * 2;
+	case 1:
+		return val * 10;
+	case 2:
+		return val * 100;
+	}
+
+	return 0;
+}
+
+static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
+{
+	u32 threshold_ns = threshold_us * 1000;
+
+	/* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
+	if (threshold_ns < 32) {
+		*scale = 0;
+		*value = threshold_ns;
+	} else if (threshold_ns < 1024) {
+		*scale = 1;
+		*value = threshold_ns >> 5;
+	} else if (threshold_ns < 32768) {
+		*scale = 2;
+		*value = threshold_ns >> 10;
+	} else if (threshold_ns < 1048576) {
+		*scale = 3;
+		*value = threshold_ns >> 15;
+	} else if (threshold_ns < 33554432) {
+		*scale = 4;
+		*value = threshold_ns >> 20;
+	} else {
+		*scale = 5;
+		*value = threshold_ns >> 25;
+	}
+}
+
+/* Calculate L1.2 PM substate timing parameters */
+static void aspm_calc_l1ss_info(struct pci_dev *child, struct pci_dev *parent)
+{
+	u32 val1, val2, scale1, scale2;
+	u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
+	u32 ctl1 = 0, ctl2 = 0;
+	u32 pctl1, pctl2, cctl1, cctl2;
+	u32 pl1_2_enables, cl1_2_enables;
+	u32 parent_l1ss_cap, child_l1ss_cap;
+
+	/* Setup L1 substate */
+	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
+			      &parent_l1ss_cap);
+	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
+			      &child_l1ss_cap);
+
+	/* Choose the greater of the two Port Common_Mode_Restore_Times */
+	val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+	val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
+	t_common_mode = max(val1, val2);
+
+	/* Choose the greater of the two Port T_POWER_ON times */
+	val1   = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+	scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+	val2   = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
+	scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
+
+	if (calc_l1ss_pwron(parent, scale1, val1) >
+	    calc_l1ss_pwron(child, scale2, val2)) {
+		ctl2 |= scale1 | (val1 << 3);
+		t_power_on = calc_l1ss_pwron(parent, scale1, val1);
+	} else {
+		ctl2 |= scale2 | (val2 << 3);
+		t_power_on = calc_l1ss_pwron(child, scale2, val2);
+	}
+
+	/* Set LTR_L1.2_THRESHOLD to the time required to transition the
+	 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
+	 * downstream devices report (via LTR) that they can tolerate at
+	 * least that much latency.
+	 *
+	 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
+	 * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
+	 * least 4us.
+	 */
+	l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
+	encode_l12_threshold(l1_2_threshold, &scale, &value);
+	ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
+
+	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
+	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
+	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
+	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
+
+	if (ctl1 == pctl1 && ctl1 == cctl1 &&
+	    ctl2 == pctl2 && ctl2 == cctl2)
+		return;
+
+	/* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
+	pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+	cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
+
+	if (pl1_2_enables || cl1_2_enables) {
+		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
+					PCI_L1SS_CTL1_L1_2_MASK, 0);
+		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+					PCI_L1SS_CTL1_L1_2_MASK, 0);
+	}
+
+	/* Program T_POWER_ON times in both ports */
+	pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
+	pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
+
+	/* Program Common_Mode_Restore_Time in upstream device */
+	pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
+				PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
+
+	/* Program LTR_L1.2_THRESHOLD time in both ports */
+	pci_clear_and_set_dword(parent,	parent->l1ss + PCI_L1SS_CTL1,
+				PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
+	pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
+				PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
+				PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
+
+	if (pl1_2_enables || cl1_2_enables) {
+		pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
+					pl1_2_enables);
+		pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
+					cl1_2_enables);
+	}
+}
+
+static void rockchip_pcie_bus_l1ss_enable_dev(char *device, struct pci_dev *dev, bool enable)
+{
+	u32 l1ssctrl_before;
+	u32 l1ssctrl_after = 0;
+	u8 l1ss_ep;
+
+	/* Extendend Capacility Reg */
+	l1ssctrl_before = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
+							PCI_L1SS_CTL1, true, false, 0);
+	l1ss_ep = (l1ssctrl_before & PCI_L1SS_CTL1_L1SS_MASK);
+
+	if (enable) {
+		if (l1ss_ep == PCI_L1SS_CTL1_L1SS_MASK) {
+			pci_err(dev, "%s: %s already enabled,  l1ssctrl: 0x%x\n",
+			       __func__, device, l1ssctrl_before);
+			return;
+		}
+		rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
+					      true, true, (l1ssctrl_before | PCI_L1SS_CTL1_L1SS_MASK));
+	} else {
+		if (l1ss_ep == 0) {
+			pci_err(dev, "%s: %s already disabled, l1ssctrl: 0x%x\n",
+			       __func__, device, l1ssctrl_before);
+			return;
+		}
+		rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS, PCI_L1SS_CTL1,
+					      true, true, (l1ssctrl_before & (~PCI_L1SS_CTL1_L1SS_MASK)));
+	}
+	l1ssctrl_after = rockchip_pcie_pcie_access_cap(dev, PCI_EXT_CAP_ID_L1SS,
+						       PCI_L1SS_CTL1, true, false, 0);
+	pci_err(dev, "%s: %s %s, l1ssctrl_before: 0x%x l1ssctrl_after: 0x%x\n",
+	       __func__, device, (enable ? "ENABLE " : "DISABLE"),
+		l1ssctrl_before, l1ssctrl_after);
+}
+
+bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent)
+{
+	u32 parent_l1ss_cap, child_l1ss_cap;
+
+	/* Setup L1 substate */
+	pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
+			      &parent_l1ss_cap);
+	pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
+			      &child_l1ss_cap);
+
+	if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
+		parent_l1ss_cap = 0;
+	if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
+		child_l1ss_cap = 0;
+
+	if (parent_l1ss_cap && child_l1ss_cap)
+		return true;
+	else
+		return false;
+}
+EXPORT_SYMBOL(pcie_aspm_ext_is_rc_ep_l1ss_capable);
+
+void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable)
+{
+	bool ret;
+
+	/* Disable ASPM of RC and EP */
+	ret = rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, false);
+
+	if (enable) {
+		/* Enable RC then EP */
+		aspm_calc_l1ss_info(child, parent);
+		rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
+		rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
+	} else {
+		/* Disable EP then RC */
+		rockchip_pcie_bus_l1ss_enable_dev("EP", child, enable);
+		rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
+	}
+
+	/* Enable ASPM of RC and EP only if this API disabled */
+	if (ret)
+		rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, true);
+}
+EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable);
+--- /dev/null
+++ b/include/linux/aspm_ext.h
+@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright (c) 2022 Rockchip Electronics Co., Ltd. */
+
+#ifndef _ASPM_EXT_H
+#define _ASPM_EXT_H
+
+#if IS_REACHABLE(CONFIG_PCIEASPM_EXT)
+bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent);
+void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable);
+#else
+static inline bool pcie_aspm_ext_is_rc_ep_l1ss_capable(struct pci_dev *child, struct pci_dev *parent) { return false; }
+static inline void pcie_aspm_ext_l1ss_enable(struct pci_dev *child, struct pci_dev *parent, bool enable) {}
+#endif
+
+#endif
--- a/patches-6.12/221-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
+++ b/patches-6.12/221-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
@ -0,0 +1,24 @@
+From a6c71606de486944c5fb028f47604fb22292312b Mon Sep 17 00:00:00 2001
+From: Jon Lin <jon.lin@rock-chips.com>
+Date: Fri, 24 Jun 2022 21:32:11 +0800
+Subject: [PATCH] PCI: aspm_ext: Re-enable LRT for L1SS after power loss
+
+Change-Id: Iedb72ee74660a8f11f38895e06766c3b77728ba3
+Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
+---
+ drivers/pci/pcie/aspm_ext.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/pci/pcie/aspm_ext.c
+++ b/drivers/pci/pcie/aspm_ext.c
+@@ -322,6 +322,10 @@ void pcie_aspm_ext_l1ss_enable(struct pc
+ 	ret = rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, false);
+ 
+ 	if (enable) {
+		/* LRT enable bits loss after wifi off, enable it after power on */
+		if (parent->ltr_path)
+			pcie_capability_set_word(parent, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN);
+
+ 		/* Enable RC then EP */
+ 		aspm_calc_l1ss_info(child, parent);
+ 		rockchip_pcie_bus_l1ss_enable_dev("RC", parent, enable);
--- a/patches-6.12/222-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
+++ b/patches-6.12/222-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
@ -0,0 +1,38 @@
+From cf03561e5ec9f2f8b41a992f3b8ca19b9c3b9e47 Mon Sep 17 00:00:00 2001
+From: Tao Huang <huangtao@rock-chips.com>
+Date: Fri, 15 Jul 2022 20:56:15 +0800
+Subject: [PATCH] PCI: aspm_ext: Fix Add missing MODULE_LICENSE()
+
+ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/pcie/aspm_ext.o
+
+Signed-off-by: Tao Huang <huangtao@rock-chips.com>
+Change-Id: Id365aba7a73f02cc2c61882b46937250e64af01c
+---
+ drivers/pci/pcie/aspm_ext.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/pcie/aspm_ext.c
+++ b/drivers/pci/pcie/aspm_ext.c
+@@ -6,6 +6,7 @@
+  */
+ 
+ #include <linux/kernel.h>
+#include <linux/module.h>
+ #include <linux/pci.h>
+ #include <linux/aspm_ext.h>
+ #include <linux/errno.h>
+@@ -95,7 +96,7 @@ static bool rockchip_pcie_bus_aspm_enabl
+ 	return true;
+ }
+ 
+-bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
+static bool rockchip_pcie_bus_aspm_enable_rc_ep(struct pci_dev *child, struct pci_dev *parent, bool enable)
+ {
+ 	bool ret;
+ 
+@@ -341,3 +342,5 @@ void pcie_aspm_ext_l1ss_enable(struct pc
+ 		rockchip_pcie_bus_aspm_enable_rc_ep(child, parent, true);
+ }
+ EXPORT_SYMBOL(pcie_aspm_ext_l1ss_enable);
+
+MODULE_LICENSE("GPL");
--- a/patches-6.12/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
+++ b/patches-6.12/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz.patch
@ -0,0 +1,32 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -35,6 +35,14 @@
+ 			opp-hz = /bits/ 64 <1416000000>;
+ 			opp-microvolt = <1125000 1125000 1250000>;
+ 		};
+		opp06 {
+			opp-hz = /bits/ 64 <1608000000>;
+			opp-microvolt = <1225000>;
+		};
+		opp07 {
+			opp-hz = /bits/ 64 <1800000000>;
+			opp-microvolt = <1275000>;
+		};
+ 	};
+ 
+ 	cluster1_opp: opp-table-1 {
+@@ -74,6 +82,14 @@
+ 			opp-hz = /bits/ 64 <1800000000>;
+ 			opp-microvolt = <1200000 1200000 1250000>;
+ 		};
+		opp08 {
+			opp-hz = /bits/ 64 <2016000000>;
+			opp-microvolt = <1250000>;
+		};
+		opp09 {
+			opp-hz = /bits/ 64 <2208000000>;
+			opp-microvolt = <1325000>;
+		};
+ 	};
+ 
+ 	gpu_opp_table: opp-table-2 {
--- a/patches-6.12/993-rockchip-rk356x-adjust-CPU-voltage.patch
+++ b/patches-6.12/993-rockchip-rk356x-adjust-CPU-voltage.patch
@ -0,0 +1,116 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -272,7 +272,7 @@
+ &cpu0_opp_table {
+ 	opp-1992000000 {
+ 		opp-hz = /bits/ 64 <1992000000>;
+-		opp-microvolt = <1150000 1150000 1150000>;
+		opp-microvolt = <1250000>;
+ 	};
+ };
+ 
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -134,39 +134,39 @@
+ 
+ 		opp-408000000 {
+ 			opp-hz = /bits/ 64 <408000000>;
+-			opp-microvolt = <900000 900000 1150000>;
+			opp-microvolt = <1000000 975000 1150000>;
+ 			clock-latency-ns = <40000>;
+ 		};
+ 
+ 		opp-600000000 {
+ 			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <900000 900000 1150000>;
+			opp-microvolt = <1000000 975000 1150000>;
+ 		};
+ 
+ 		opp-816000000 {
+ 			opp-hz = /bits/ 64 <816000000>;
+-			opp-microvolt = <900000 900000 1150000>;
+			opp-microvolt = <1000000 975000 1150000>;
+ 			opp-suspend;
+ 		};
+ 
+ 		opp-1104000000 {
+ 			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <900000 900000 1150000>;
+			opp-microvolt = <1000000 975000 1150000>;
+ 		};
+ 
+ 		opp-1416000000 {
+ 			opp-hz = /bits/ 64 <1416000000>;
+-			opp-microvolt = <900000 900000 1150000>;
+			opp-microvolt = <1000000 975000 1150000>;
+ 		};
+ 
+ 		opp-1608000000 {
+ 			opp-hz = /bits/ 64 <1608000000>;
+-			opp-microvolt = <975000 975000 1150000>;
+			opp-microvolt = <1000000 1000000 1150000>;
+ 		};
+ 
+ 		opp-1800000000 {
+ 			opp-hz = /bits/ 64 <1800000000>;
+-			opp-microvolt = <1050000 1050000 1150000>;
+			opp-microvolt = <1150000 1000000 1250000>;
+ 		};
+ 	};
+ 
+--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -162,16 +162,17 @@ static struct rockchip_pll_rate_table rk
+ }
+ 
+ static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
+	RK3568_CPUCLK_RATE(1992000000, 0, 1, 8, 8, 8, 8),
+ 	RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
+ 	RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
+-	RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
+	RK3568_CPUCLK_RATE(1608000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1584000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1560000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1536000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1512000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1488000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1464000000, 0, 1, 6, 6, 6, 6),
+	RK3568_CPUCLK_RATE(1440000000, 0, 1, 6, 6, 6, 6),
+ 	RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
+ 	RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
+ 	RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
+@@ -181,17 +182,17 @@ static struct rockchip_cpuclk_rate_table
+ 	RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
+ 	RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
+ 	RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
+-	RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
+	RK3568_CPUCLK_RATE(1200000000, 0, 1, 4, 4, 4, 4),
+	RK3568_CPUCLK_RATE(1104000000, 0, 1, 4, 4, 4, 4),
+	RK3568_CPUCLK_RATE(1008000000, 0, 1, 4, 4, 4, 4),
+ 	RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
+-	RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
+	RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 2),
+	RK3568_CPUCLK_RATE(696000000, 0, 1, 2, 2, 2, 2),
+	RK3568_CPUCLK_RATE(600000000, 0, 1, 2, 2, 2, 2),
+	RK3568_CPUCLK_RATE(408000000, 0, 1, 1, 1, 1, 1),
+	RK3568_CPUCLK_RATE(312000000, 0, 1, 1, 1, 1, 1),
+	RK3568_CPUCLK_RATE(216000000, 0, 1, 1, 1, 1, 1),
+	RK3568_CPUCLK_RATE(96000000, 0, 1, 1, 1, 1, 1),
+ };
+ 
+ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
--- a/patches-6.6/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch
+++ b/patches-6.6/012-rk356x-add-dwc3-xhci-usb-trb-quirk.patch
@ -18,7 +18,7 @@
 
 --- a/drivers/usb/dwc3/core.c
 +++ b/drivers/usb/dwc3/core.c
-@@ -1591,6 +1591,8 @@ static void dwc3_get_properties(struct d
+@@ -1620,6 +1620,8 @@ static void dwc3_get_properties(struct d
 				"snps,dis-del-phy-power-chg-quirk");
 	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
 				"snps,dis-tx-ipgap-linecheck-quirk");
@ -29,7 +29,7 @@
 	dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
 --- a/drivers/usb/dwc3/core.h
 +++ b/drivers/usb/dwc3/core.h
-@@ -1107,6 +1107,9 @@ struct dwc3_scratchpad_array {
+@@ -1108,6 +1108,9 @@ struct dwc3_scratchpad_array {
  *			change quirk.
  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
  *			check during HS transmit.
@ -39,7 +39,7 @@
  * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
  *			generation after resume from suspend.
  * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
-@@ -1333,6 +1336,7 @@ struct dwc3 {
+@@ -1337,6 +1340,7 @@ struct dwc3 {
 	unsigned		dis_u2_freeclk_exists_quirk:1;
 	unsigned		dis_del_phy_power_chg_quirk:1;
 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
@ -73,7 +73,7 @@
 	}
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
-@@ -3637,6 +3637,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3651,6 +3651,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
 	bool more_trbs_coming = true;
 	bool need_zero_pkt = false;
 	bool first_trb = true;
@ -81,7 +81,7 @@
 	unsigned int num_trbs;
 	unsigned int start_cycle, num_sgs = 0;
 	unsigned int enqd_len, block_len, trb_buff_len, full_len;
-@@ -3673,6 +3674,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3687,6 +3688,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
 	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
 		need_zero_pkt = true;
 
@ -95,7 +95,7 @@
 	td = &urb_priv->td[0];
 
 	/*
-@@ -3701,6 +3709,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3715,6 +3723,13 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
 			first_trb = false;
 			if (start_cycle == 0)
 				field |= TRB_CYCLE;
@ -109,7 +109,7 @@
 		} else
 			field |= ring->cycle_state;
 
-@@ -3709,6 +3724,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
+@@ -3723,6 +3738,8 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
 		 */
 		if (enqd_len + trb_buff_len < full_len) {
 			field |= TRB_CHAIN;
@ -120,7 +120,7 @@
 						  &trb_buff_len,
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1530,7 +1530,11 @@ static inline const char *xhci_trb_type_
+@@ -1275,7 +1275,11 @@ static inline const char *xhci_trb_type_
 #define TRB_SEGMENT_SIZE	(TRBS_PER_SEGMENT*16)
 #define TRB_SEGMENT_SHIFT	(ilog2(TRB_SEGMENT_SIZE))
 /* TRB buffer pointers can't cross 64KB boundaries */
@ -132,7 +132,7 @@
 #define TRB_MAX_BUFF_SIZE	(1 << TRB_MAX_BUFF_SHIFT)
 /* How much data is left before the 64KB boundary? */
 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr)	(TRB_MAX_BUFF_SIZE - \
-@@ -1855,6 +1859,7 @@ struct xhci_hcd {
+@@ -1600,6 +1604,7 @@ struct xhci_hcd {
 #define XHCI_STATE_HALTED	(1 << 1)
 #define XHCI_STATE_REMOVING	(1 << 2)
 	unsigned long long	quirks;
--- a/patches-6.6/014-rockchip-add-pwm-fan-controller-for-nanopi-r2s-r4s.patch
+++ b/patches-6.6/014-rockchip-add-pwm-fan-controller-for-nanopi-r2s-r4s.patch
@ -0,0 +1,45 @@
+From 508a0a0d4e2e7b547950b2adb15594a75654708f Mon Sep 17 00:00:00 2001
+From: sbwml <admin@cooluc.com>
+Date: Mon, 2 Dec 2024 10:34:33 +0800
+Subject: [PATCH] rockchip: add pwm-fan controller for nanopi r2s/r4s
+
+Signed-off-by: sbwml <admin@cooluc.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 8 ++++++++
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -114,6 +114,14 @@
+ 		regulator-boot-on;
+ 		vin-supply = <&vdd_5v>;
+ 	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 18 60 100 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vdd_5v>;
+		pwms = <&pwm2 0 50000 0>;
+	};
+ };
+ 
+ &cpu0 {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -69,6 +69,14 @@
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 18 60 100 255>;
+		#cooling-cells = <2>;
+		fan-supply = <&vdd_5v>;
+		pwms = <&pwm1 0 50000 0>;
+	};
+ };
+ 
+ &emmc_phy {
--- a/patches-6.6/033-01-v6.7-drm-rockchip-vop-Add-rv1126-vop_lite-support.patch
+++ b/patches-6.6/033-01-v6.7-drm-rockchip-vop-Add-rv1126-vop_lite-support.patch
@ -17,7 +17,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20230731110012.2913742-7-jag

 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
 +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
-@@ -1120,6 +1120,59 @@ static const struct vop_data rk3328_vop
+@@ -1122,6 +1122,59 @@ static const struct vop_data rk3328_vop
 	.max_output = { 4096, 2160 },
 };
 
@ -77,7 +77,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20230731110012.2913742-7-jag
 static const struct of_device_id vop_driver_dt_match[] = {
 	{ .compatible = "rockchip,rk3036-vop",
 	  .data = &rk3036_vop },
-@@ -1147,6 +1200,8 @@ static const struct of_device_id vop_dri
+@@ -1149,6 +1202,8 @@ static const struct of_device_id vop_dri
 	  .data = &rk3228_vop },
 	{ .compatible = "rockchip,rk3328-vop",
 	  .data = &rk3328_vop },
--- a/patches-6.6/033-03-v6.7-drm-rockchip-vop-Use-cleanup-helper-directly-as-destroy.patch
+++ b/patches-6.6/033-03-v6.7-drm-rockchip-vop-Use-cleanup-helper-directly-as-destroy.patch
@ -39,7 +39,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-3-jon
 	.reset = drm_atomic_helper_plane_reset,
 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
-@@ -1610,11 +1605,6 @@ static const struct drm_crtc_helper_func
+@@ -1614,11 +1609,6 @@ static const struct drm_crtc_helper_func
 	.atomic_disable = vop_crtc_atomic_disable,
 };
 
@ -51,7 +51,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-3-jon
 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
 {
 	struct rockchip_crtc_state *rockchip_state;
-@@ -1722,7 +1712,7 @@ vop_crtc_verify_crc_source(struct drm_cr
+@@ -1726,7 +1716,7 @@ vop_crtc_verify_crc_source(struct drm_cr
 static const struct drm_crtc_funcs vop_crtc_funcs = {
 	.set_config = drm_atomic_helper_set_config,
 	.page_flip = drm_atomic_helper_page_flip,
@ -60,7 +60,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-3-jon
 	.reset = vop_crtc_reset,
 	.atomic_duplicate_state = vop_crtc_duplicate_state,
 	.atomic_destroy_state = vop_crtc_destroy_state,
-@@ -1973,7 +1963,7 @@ static void vop_destroy_crtc(struct vop
+@@ -1977,7 +1967,7 @@ static void vop_destroy_crtc(struct vop
 	 */
 	list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
 				 head)
--- a/patches-6.6/033-14-v6.7-drm-rockchip-vop-Add-NV15-NV20-and-NV30-support.patch
+++ b/patches-6.6/033-14-v6.7-drm-rockchip-vop-Add-NV15-NV20-and-NV30-support.patch
@ -108,7 +108,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona
 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
 +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -186,6 +186,7 @@ struct vop_win_phy {
+@@ -187,6 +187,7 @@ struct vop_win_phy {
 	struct vop_reg enable;
 	struct vop_reg gate;
 	struct vop_reg format;
@ -145,7 +145,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona
 static const uint64_t format_modifiers_win_full[] = {
 	DRM_FORMAT_MOD_LINEAR,
 	DRM_FORMAT_MOD_INVALID,
-@@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_
+@@ -629,11 +649,12 @@ static const struct vop_scl_regs rk3288_
 
 static const struct vop_win_phy rk3288_win01_data = {
 	.scl = &rk3288_win_full_scl,
@ -160,7 +160,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona
 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
-@@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data
+@@ -938,13 +959,38 @@ static const struct vop_win_yuv2yuv_data
 
 };
 
@ -202,7 +202,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona
 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 	.uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15),
 	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
-@@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_w
+@@ -967,9 +1013,9 @@ static const struct vop_win_phy rk3399_w
  * AFBC on the primary plane.
  */
 static const struct vop_win_data rk3399_vop_win_data[] = {
@ -214,7 +214,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona
 	  .type = DRM_PLANE_TYPE_OVERLAY },
 	{ .base = 0x00, .phy = &rk3368_win23_data,
 	  .type = DRM_PLANE_TYPE_OVERLAY },
-@@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_
+@@ -1101,11 +1147,11 @@ static const struct vop_intr rk3328_vop_
 };
 
 static const struct vop_win_data rk3328_vop_win_data[] = {
--- a/patches-6.6/033-19-v6.8-drm-rockchip-move-output-interface-related-definition-to.patch
+++ b/patches-6.6/033-19-v6.8-drm-rockchip-move-output-interface-related-definition-to.patch
@ -114,7 +114,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231211115627.1784735-1-and
 struct iommu_domain;
 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
 +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
-@@ -277,18 +277,6 @@ struct vop_data {
+@@ -278,18 +278,6 @@ struct vop_data {
 /* dst alpha ctrl define */
 #define DST_FACTOR_M0(x)		(((x) & 0x7) << 6)
 
--- a/patches-6.6/034-20-v6.7-drm-sched-Convert-the-GPU-scheduler-to-variable-number-of.patch
+++ b/patches-6.6/034-20-v6.7-drm-sched-Convert-the-GPU-scheduler-to-variable-number-of.patch
@ -156,7 +156,7 @@ Link: https://lore.kernel.org/r/20231023032251.164775-1-luben.tuikov@amd.com
 
 	init_completion(&entity->entity_idle);
 
-@@ -533,7 +545,7 @@ void drm_sched_entity_select_rq(struct d
+@@ -535,7 +547,7 @@ void drm_sched_entity_select_rq(struct d
 
 	spin_lock(&entity->rq_lock);
 	sched = drm_sched_pick_best(entity->sched_list, entity->num_sched_list);
--- a/patches-6.6/034-21-v6.8-drm-sched-Add-drm_sched_wqueue_-helpers.patch
+++ b/patches-6.6/034-21-v6.8-drm-sched-Add-drm_sched_wqueue_-helpers.patch
@ -92,7 +92,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 
 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
 +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
-@@ -4614,7 +4614,7 @@ bool amdgpu_device_has_job_running(struc
+@@ -4615,7 +4615,7 @@ bool amdgpu_device_has_job_running(struc
 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 		struct amdgpu_ring *ring = adev->rings[i];
 
@ -101,7 +101,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 			continue;
 
 		spin_lock(&ring->sched.job_list_lock);
-@@ -4756,7 +4756,7 @@ int amdgpu_device_pre_asic_reset(struct
+@@ -4757,7 +4757,7 @@ int amdgpu_device_pre_asic_reset(struct
 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 		struct amdgpu_ring *ring = adev->rings[i];
 
@ -110,7 +110,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 			continue;
 
 		/* Clear job fence from fence drv to avoid force_completion
-@@ -5296,7 +5296,7 @@ int amdgpu_device_gpu_recover(struct amd
+@@ -5297,7 +5297,7 @@ int amdgpu_device_gpu_recover(struct amd
 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 			struct amdgpu_ring *ring = tmp_adev->rings[i];
 
@ -119,7 +119,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 				continue;
 
 			drm_sched_stop(&ring->sched, job ? &job->base : NULL);
-@@ -5371,7 +5371,7 @@ skip_hw_reset:
+@@ -5372,7 +5372,7 @@ skip_hw_reset:
 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 			struct amdgpu_ring *ring = tmp_adev->rings[i];
 
@ -128,7 +128,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 				continue;
 
 			drm_sched_start(&ring->sched, true);
-@@ -5697,7 +5697,7 @@ pci_ers_result_t amdgpu_pci_error_detect
+@@ -5698,7 +5698,7 @@ pci_ers_result_t amdgpu_pci_error_detect
 		for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 			struct amdgpu_ring *ring = adev->rings[i];
 
@ -137,7 +137,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 				continue;
 
 			drm_sched_stop(&ring->sched, NULL);
-@@ -5825,7 +5825,7 @@ void amdgpu_pci_resume(struct pci_dev *p
+@@ -5826,7 +5826,7 @@ void amdgpu_pci_resume(struct pci_dev *p
 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 		struct amdgpu_ring *ring = adev->rings[i];
 
--- a/patches-6.6/034-25-v6.8-drm-sched-Drop-suffix-from-drm_sched_wakeup_if_can_queue.patch
+++ b/patches-6.6/034-25-v6.8-drm-sched-Drop-suffix-from-drm_sched_wakeup_if_can_queue.patch
@ -22,7 +22,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>

 --- a/drivers/gpu/drm/scheduler/sched_entity.c
 +++ b/drivers/gpu/drm/scheduler/sched_entity.c
-@@ -370,7 +370,7 @@ static void drm_sched_entity_wakeup(stru
+@@ -372,7 +372,7 @@ static void drm_sched_entity_wakeup(stru
 		container_of(cb, struct drm_sched_entity, cb);
 
 	drm_sched_entity_clear_dep(f, cb);
@ -31,7 +31,7 @@ Signed-off-by: Luben Tuikov <ltuikov89@gmail.com>
 }
 
 /**
-@@ -602,7 +602,7 @@ void drm_sched_entity_push_job(struct dr
+@@ -604,7 +604,7 @@ void drm_sched_entity_push_job(struct dr
 		if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
 			drm_sched_rq_update_fifo(entity, submit_ts);
 
--- a/patches-6.6/034-26-v6.8-drm-sched-Qualify-drm_sched_wakeup-by.patch
+++ b/patches-6.6/034-26-v6.8-drm-sched-Qualify-drm_sched_wakeup-by.patch
@ -20,7 +20,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231110000123.72565-2-ltuik

 --- a/drivers/gpu/drm/scheduler/sched_entity.c
 +++ b/drivers/gpu/drm/scheduler/sched_entity.c
-@@ -370,7 +370,7 @@ static void drm_sched_entity_wakeup(stru
+@@ -372,7 +372,7 @@ static void drm_sched_entity_wakeup(stru
 		container_of(cb, struct drm_sched_entity, cb);
 
 	drm_sched_entity_clear_dep(f, cb);
@ -29,7 +29,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231110000123.72565-2-ltuik
 }
 
 /**
-@@ -602,7 +602,7 @@ void drm_sched_entity_push_job(struct dr
+@@ -604,7 +604,7 @@ void drm_sched_entity_push_job(struct dr
 		if (drm_sched_policy == DRM_SCHED_POLICY_FIFO)
 			drm_sched_rq_update_fifo(entity, submit_ts);
 
--- a/patches-6.6/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch
+++ b/patches-6.6/102-net-phy-realtek-RTL8211-add-LED-configuration-from-OF.patch
@ -18,7 +18,7 @@ Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
 #define RTL8211F_PHYCR1				0x18
 #define RTL8211F_PHYCR2				0x19
 #define RTL8211F_INSR				0x1d
-@@ -376,6 +378,7 @@ static int rtl8211f_config_init(struct p
+@@ -379,6 +381,7 @@ static int rtl8211f_config_init(struct p
 	struct rtl821x_priv *priv = phydev->priv;
 	struct device *dev = &phydev->mdio.dev;
 	u16 val_txdly, val_rxdly;
@ -26,7 +26,7 @@ Subject: [PATCH] net: phy: realtek: add LED configuration from OF for 8211f
 	int ret;
 
 	ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
-@@ -451,6 +454,15 @@ static int rtl8211f_config_init(struct p
+@@ -454,6 +457,15 @@ static int rtl8211f_config_init(struct p
 			return ret;
 		}
 
--- a/patches-6.6/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
+++ b/patches-6.6/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
@ -1,6 +1,6 @@
 --- a/arch/arm64/Kconfig
 +++ b/arch/arm64/Kconfig
-@@ -1285,6 +1285,14 @@ config SOCIONEXT_SYNQUACER_PREITS
+@@ -1286,6 +1286,14 @@ config SOCIONEXT_SYNQUACER_PREITS
 
 	  If unsure, say Y.
 
--- a/patches-6.6/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
+++ b/patches-6.6/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
@ -7,100 +7,67 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
 1 file changed, 65 insertions(+), 5 deletions(-)

+--- a/drivers/irqchip/irq-gic-common.h
+++ b/drivers/irqchip/irq-gic-common.h
+@@ -32,5 +32,6 @@ void gic_enable_of_quirks(const struct d
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING    (1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED     (1 << 1)
+ #define RDIST_FLAGS_FORCE_NON_SHAREABLE        (1 << 2)
+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE       (1 << 3)
+ 
+ #endif /* _IRQ_GIC_COMMON_H */
 --- a/drivers/irqchip/irq-gic-v3-its.c
 +++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -42,6 +42,7 @@
- #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
- #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
- #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
-+#define ITS_FLAGS_FORCE_NO_LOCAL_CACHE		(1ULL << 2)
- #define ITS_FLAGS_FORCE_NON_SHAREABLE		(1ULL << 3)
- 
- #define RD_LOCAL_LPI_ENABLED                    BIT(0)
-@@ -2186,6 +2187,11 @@ static struct page *its_allocate_prop_ta
+@@ -2192,6 +2192,11 @@ static struct page *its_allocate_prop_ta
 {
 	struct page *prop_page;
 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
+		pr_debug("ITS ALLOCATE PROP WORKAROUND\n");
 +		gfp_flags |= GFP_DMA;
 +	}
 +
 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
 	if (!prop_page)
 		return NULL;
-@@ -2309,6 +2315,7 @@ static int its_setup_baser(struct its_no
+@@ -2314,6 +2319,7 @@ static int its_setup_baser(struct its_no
+ 	u64 baser_phys, tmp;
 	u32 alloc_pages, psz;
 	struct page *page;
- 	void *base;
 +	gfp_t gfp_flags;
+ 	void *base;
 
 	psz = baser->psz;
- 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
-@@ -2320,7 +2327,10 @@ static int its_setup_baser(struct its_no
+@@ -2326,7 +2332,10 @@ static int its_setup_baser(struct its_no
 		order = get_order(GITS_BASER_PAGES_MAX * psz);
 	}
 
 -	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
 +	gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		gfp_flags |= GFP_DMA;
 +	page = alloc_pages_node(its->numa_node, gfp_flags, order);
 	if (!page)
 		return -ENOMEM;
 
-@@ -2370,6 +2380,13 @@ retry_baser:
- 	its_write_baser(its, baser, val);
- 	tmp = baser->val;
- 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+		if (tmp & GITS_BASER_SHAREABILITY_MASK)
-+			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
-+		else
-+			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
-+	}
-+
- 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
- 		/*
- 		 * Shareability didn't stick. Just use
-@@ -2960,6 +2977,10 @@ static struct page *its_allocate_pending
+@@ -2966,6 +2975,10 @@ static struct page *its_allocate_pending
 {
 	struct page *pend_page;
 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +		gfp_flags |= GFP_DMA;
 +	}
 +
 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
 				get_order(LPI_PENDBASE_SZ));
 	if (!pend_page)
-@@ -3115,6 +3136,9 @@ static void its_cpu_init_lpis(void)
- 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
- 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
- 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
-+
- 	if (!rdists_support_shareable())
- 		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
- 
-@@ -3142,6 +3166,9 @@ static void its_cpu_init_lpis(void)
- 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
- 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
- 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
-+
- 	if (!rdists_support_shareable())
- 		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
- 
-@@ -3308,7 +3335,12 @@ static bool its_alloc_table_entry(struct
+@@ -3314,7 +3327,12 @@ static bool its_alloc_table_entry(struct
 
 	/* Allocate memory for 2nd level table */
 	if (!table[idx]) {
 -		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
 +		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+		if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE) {
+		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
 +			gfp_flags |= GFP_DMA;
 +		}
 +
@ -108,28 +75,28 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 					get_order(baser->psz));
 		if (!page)
 			return false;
-@@ -3397,6 +3429,7 @@ static struct its_device *its_create_dev
- 	int nr_lpis;
- 	int nr_ites;
- 	int sz;
+@@ -3398,6 +3416,7 @@ static struct its_device *its_create_dev
+ 	unsigned long *lpi_map = NULL;
+ 	unsigned long flags;
+ 	u16 *col_map = NULL;
 +	gfp_t gfp_flags;
- 
- 	if (!its_alloc_device_table(its, dev_id))
- 		return NULL;
-@@ -3404,7 +3437,11 @@ static struct its_device *its_create_dev
+ 	void *itt;
+ 	int lpi_base;
+ 	int nr_lpis;
+@@ -3410,7 +3429,11 @@ static struct its_device *its_create_dev
 	if (WARN_ON(!is_power_of_2(nvecs)))
 		nvecs = roundup_pow_of_two(nvecs);
 
 -	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 +	gfp_flags = GFP_KERNEL;
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
 +		gfp_flags |= GFP_DMA;
 +
 +	dev = kzalloc(sizeof(*dev), gfp_flags);
 	/*
 	 * Even if the device wants a single LPI, the ITT must be
 	 * sized as a power of two (and you need at least one bit...).
-@@ -3412,7 +3449,7 @@ static struct its_device *its_create_dev
+@@ -3418,7 +3441,7 @@ static struct its_device *its_create_dev
 	nr_ites = max(2, nvecs);
 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
@ -138,44 +105,50 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 	if (alloc_lpis) {
 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
 		if (lpi_map)
-@@ -4752,6 +4789,13 @@ static bool its_set_non_coherent(void *d
+@@ -4742,6 +4765,21 @@ static bool __maybe_unused its_enable_qu
 	return true;
 }
 
-+static bool __maybe_unused its_enable_quirk_rk3568(void *data)
+static bool __maybe_unused its_enable_rk3568001(void *data)
 +{
-+	gic_rdists->flags |= ITS_FLAGS_FORCE_NO_LOCAL_CACHE;
+	struct its_node *its = data;
+
+	if (!of_machine_is_compatible("rockchip,rk3566") &&
+	    !of_machine_is_compatible("rockchip,rk3568"))
+		return false;
+
+	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
+	gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE |
+			     RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
 +
 +	return true;
 +}
 +
- static const struct gic_quirk its_quirks[] = {
- #ifdef CONFIG_CAVIUM_ERRATUM_22375
- 	{
-@@ -4806,6 +4850,14 @@ static const struct gic_quirk its_quirks
- 		.init   = its_enable_rk3588001,
- 	},
+ static bool __maybe_unused its_enable_rk3588001(void *data)
+ {
+ 	struct its_node *its = data;
+@@ -4812,6 +4850,12 @@ static const struct gic_quirk its_quirks
 #endif
-+#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
-+	{
-+		.desc	= "ITS: Rockchip erratum 114514",
-+		.iidr	= 0x0201743b,
-+		.mask	= 0xffffffff,
-+		.init	= its_enable_quirk_rk3568,
-+	},
-+#endif
+ #ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
 	{
- 		.desc   = "ITS: non-coherent attribute",
- 		.property = "dma-noncoherent",
-@@ -5067,6 +5119,7 @@ static int __init its_probe_one(struct i
+		.desc   = "ITS: Rockchip erratum RK3568001",
+		.iidr   = 0x0201743b,
+		.mask   = 0xffffffff,
+		.init   = its_enable_rk3568001,
+	},
+	{
+ 		.desc   = "ITS: Rockchip erratum RK3588001",
+ 		.iidr   = 0x0201743b,
+ 		.mask   = 0xffffffff,
+@@ -5077,6 +5121,7 @@ static int __init its_probe_one(struct i
+ {
+ 	u64 baser, tmp;
 	struct page *page;
+	gfp_t gfp_flags;
 	u32 ctlr;
 	int err;
-+	gfp_t gfp_flags;
 
- 	its_enable_quirks(its);
- 
-@@ -5100,7 +5153,9 @@ static int __init its_probe_one(struct i
+@@ -5112,7 +5157,9 @@ static int __init its_probe_one(struct i
 		}
 	}
 
@ -186,13 +159,3 @@ Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
 				get_order(ITS_CMD_QUEUE_SZ));
 	if (!page) {
 		err = -ENOMEM;
-@@ -5126,6 +5181,9 @@ static int __init its_probe_one(struct i
- 	gits_write_cbaser(baser, its->base + GITS_CBASER);
- 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
- 
-+	if (gic_rdists->flags & ITS_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
-+
- 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
- 		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
-
Author	SHA1	Message	Date
sbwml	d22fd45a87	config-6.12: enable ROCKCHIP DFI DEVFREQ event Driver Signed-off-by: sbwml <admin@cooluc.com>	2024-12-07 00:31:27 +08:00
sbwml	97218a65c3	rockchip: add pwm-fan controller for nanopi r2s/r4s Signed-off-by: sbwml <admin@cooluc.com>	2024-12-02 10:47:33 +08:00
sbwml	4d6fb5ddf5	rockchip: update dts for nanopi r5s Signed-off-by: sbwml <admin@cooluc.com>	2024-11-29 06:23:13 +08:00
sbwml	dd5a77edf8	rockchip: drop pwm-fan scripts Signed-off-by: sbwml <admin@cooluc.com>	2024-11-25 21:04:25 +08:00
sbwml	421565bd24	rockchip: default kernel 6.12 Signed-off-by: sbwml <admin@cooluc.com>	2024-11-07 08:55:59 +08:00
sbwml	e82b39093d	rockchip: fixes rk3568 pcie msi issue Signed-off-by: sbwml <admin@cooluc.com>	2024-10-17 05:47:39 +08:00
sbwml	3623c69f46	rockchip: patches-6.6: refresh patches Signed-off-by: sbwml <admin@cooluc.com>	2024-10-12 09:55:15 +08:00
sbwml	8d4f8a7867	rockchip: config: remove CONFIG_FORTIFY_SOURCE Signed-off-by: sbwml <admin@cooluc.com>	2024-10-06 05:02:43 +08:00
sbwml	889a7c4e57	rockchip: init linux-6.12 Signed-off-by: sbwml <admin@cooluc.com>	2024-09-30 19:01:16 +08:00
sbwml	a793154b0b	rockchip: init linux-6.11 Signed-off-by: sbwml <admin@cooluc.com>	2024-09-23 04:53:55 +08:00